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ADC1175 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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ADC1175 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 19 page ![]() Converter Electrical Characteristics (Continued) The following specifications apply for AV DD =DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, f CLK = 20MHz at 50% duty cycle. Boldface limits apply for TA =TMIN to TMAX; all other limits TA = 25˚C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units V RT Reference Top Self Bias Voltage V RT connected to VRTS V RB connected to VRBS 2.6 V V RB Reference Bottom Self Bias Voltage V RT connected to VRTS 0.6 0.55 V(min) V RB connected to VRBS 0.65 V(max) V RTS - V RBS Self Bias Voltage Delta V RT connected to VRTS, V RB connected to VRBS 2 1.89 2.15 µAmin µAmax V RT connected to VRTS, V RB connected to AVSS 2.3 V V RT -VRB Reference Voltage Delta 2 1.0 V(min) 2.8 V(max) Power Supply Characteristics IA DD Analog Supply Current DV DD =AVDD =5.25V 9.5 mA ID DD Digital Supply Current DV DD =AVDD =5.25V 2.5 mA IAV DD + IDV DD Total Operating Current DV DD AVDD =5.25V, fCLK = 20 MHz 12 17 mA DV DD AVDD =5.25V, fCLK = 30 MHz 13 DV DD =AVDD =5.25V, CLK Low (Note 10) 9.6 mA Power Consumption DV DD =AVDD =5.25V, fCLK = 20 MHz 60 85 mW DV DD =AVDD =5.25V, fCLK = 30 MHz 65 mW CLK, OE Digital Input Characteristics V IH Logical High Input Voltage DV DD =AVDD = +5.25V 3.0 V (min) V IL Logical Low Input Voltage DV DD =AVDD = +5.25V 1.0 V (max) I IH Logical High Input Current V IH =DVDD =AVDD = +5.25V 5 µA I IL Logic Low Input Current V IL = 0V, DVDD =AVDD = +5.25V −5 µA C IN Logic Input Capacitance 5 pF Digital Output Characteristics I OH High Level Output Current DV DD = 4.75V, VOH = 2.4V −1.1 mA (min) I OL Low Level Output Current DV DD = 4.75V, VOL = 0.4V 1.6 mA (max) I OZH, I OZL Tri-State® Leakage Current DV DD = 5.25V OE=DV DD,VOL = 0VorV OH =DVDD ±20 µA AC Electrical Characteristics f C1 Maximum Conversion Rate 30 20 MHz(min) f C2 Minimum Conversion Rate 1 MHz t OD Output Delay CLK high to data valid 19 ns(max) Pipeline Delay (Latency) 2.5 Clock Cycles t DS Sampling (Aperture) Delay CLK low to acquisition of data 3 ns t AJ Aperture Jitter 30 ps rms t OH Output Hold Time CLK high to data invalid 10 ns t EN OE Low to Data Valid Loaded as in Figure 2 11 ns t DIS OE High to High Z State Loaded as in Figure 2 15 ns ENOB Effective Number of Bits f IN = 1.31 MHz, VIN = FS-2LSB f IN = 4.43 MHz, VIN = FS-2LSB f IN = 9.9 MHz, VIN = FS-2LSB f IN = 4.43 MHz, fCLK = 30 MHz 7.5 7.3 7.2 6.5 7.0 Bits (min) www.national.com 6 |
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