ADC1175 datasheet(7/19 Pages) NSC

7 / 19 page

Converter Electrical Characteristics (Continued)

The following specifications apply for AV

DD =DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF,

CLK = 20MHz at 50% duty cycle. Boldface limits apply for TA =TMIN to TMAX; all other limits TA = 25˚C (Notes 7, 8)

Symbol

Parameter

Conditions

Typical

(Note 9)

Limits

(Note 9)

Units

SINAD

Signal-to- Noise & Distortion

IN = 1.31 MHz, VIN = FS-2LSB

IN = 4.43 MHz, VIN = FS-2LSB

IN = 9.9 MHz, VIN = FS-2LSB

IN = 4.43 MHz, fCLK = 30 MHz

dB(min)

SNR

Signal-to- Noise Ratio

IN = 1.31 MHz, VIN = FS-2LSB

IN = 4.43 MHz, VIN = FS-2LSB

IN = 9.9 MHz, VIN = FS-2LSB

IN = 4.43 MHz, fCLK = 30 MHz

dB(min)

SFDR

Spurious Free Dynamic Range

IN = 1.31 MHz, VIN = FS-2LSB

IN = 4.43 MHz, VIN = FS-2LSB

IN = 9.9 MHz, VIN = FS-2LSB

IN = 4.43 MHz, fCLK = 30 MHz

THD

Total Harmonic Distortion

IN = 1.31 MHz, VIN = FS-2LSB

IN = 4.43 MHz, VIN = FS-2LSB

IN = 9.9 MHz, VIN = FS-2LSB

IN = 4.43 MHz, fCLK = 30 MHz

−55

−57

−52

−47

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = AVSS =DVSS = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the current at that pin should

be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of

25 mA to two.

Note 4: The absolute maximum junction temperatures (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance

θJA, and the ambient temperature, TA, and can be calculated using the formula PDMAX=(TJmax - TA )/θJA. In the 24-pin

TSSOP,

θJA is 92˚C/W, so PDMAX = 1,358 mW at 25˚C and 815 mW at the maximum operating ambient temperature of 75˚C. (Typical thermal resistance, θJA,of

this part is 98˚C/W for the EIAJ SOIC). Note that the power dissipation of this device under normal operation will typically be about 101 mW (60 mW quiescent power

+ 33 mW reference ladder power+8mWdue to 1 TTL loan on each digital output. The values for maximum power dissipation listed above will be reached only when

the ADC1175 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5k

Ω resistor. Machine model is 220 pf discharged through ZERO Ω.

Note 6: See AN450, "Surface Mounting Methods and Their Effect on Product Reliability", or the section entitled "Surface Mount" found in any post 1986 National

Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this device. However, errors

in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an example, if AVDD is 4.75VDC, the full-scale input voltage must

≤4.80VDC to ensure accurate conversions.

10009210

Note 8: To guarantee accuracy, it is required that AVDD and DVDD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.

Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality

Level).

Note 10: At least two clock cycles must be presented to the ADC1175 after power up. See Section 4.0 for details.

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