PI7C7300D datasheet(34/107 Pages) PERICOM

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PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 34 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

Because read transactions to configuration space do not have side effects, all bytes in the

requested DWORD are returned, regardless of the value of the byte enable bits.

Type 0 configuration write and read transactions do not use data buffers; that is, these

transactions are completed immediately, regardless of the state of the data buffers. The

PI7C7300D ignores all Type 0 transactions initiated on the secondary interface.

4.8.2

TYPE 1 TO TYPE 0 CONVERSION

Type 1 configuration transactions are used specifically for device configuration in a

hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should

respond to a Type 1 configuration command. Type 1 configuration commands are used

when the configuration access is intended for a PCI device that resides on a PCI bus

other than the one where the Type 1 transaction is generated.

PI7C7300D performs a Type 1 to Type 0 translation when the Type 1 transaction is

generated on the primary bus and is intended for a device attached directly to the

secondary bus. PI7C7300D must convert the configuration command to a Type 0 format

so that the secondary bus device can respond to it. Type 1 to Type 0 translations are

performed only in the downstream direction; that is, PI7C7300D generates a Type 0

transaction only on the secondary bus, and never on the primary bus.

PI7C7300D responds to a Type 1 configuration transaction and translates it into a Type 0

transaction on the secondary bus when the following conditions are met during the

address phase:

The lowest two address bits on P_AD[1:0] are 01b.

The bus number in address field P_AD[23:16] is equal to the value in the secondary

bus number register in configuration space.

The bus command on P_CBE[3:0] is a configuration read or configuration write

transaction.

When PI7C7300D translates the Type 1 transaction to a Type 0 transaction on the

secondary interface, it performs the following translations to the address:

Sets the lowest two address bits on S1_AD[1:0] or S2_AD[1:0] to 00b.

Decodes the device number and drives the bit pattern specified in Table 4-6 on

S1_AD[31:16] or S2_AD[31:16] for the purpose of asserting the device’s IDSEL

signal.

Sets S1_AD[15:11] or S2_AD[15:11] to 0.

Leaves unchanged the function number and register number fields.

PI7C7300D asserts a unique address line based on the device number. These address

lines may be used as secondary bus IDSEL signals. The mapping of the address lines

depends on the device number in the Type 1 address bits P_AD[15:11]. Table 4-6

presents the mapping that PI7C7300D uses.

Table 4-6 DEVICE NUMBER TO IDSEL S1_AD OR S2_AD PIN MAPPING

Device Number

P_AD[15:11]

Secondary

IDSEL

S1_AD[31:16]

S2_AD[31:16]

S1_AD

S2_AD

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