PI7C7300D datasheet(16/107 Pages) PERICOM

16 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 16 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

Name

Pin #

Type

Description

S1_IRDY#,

S2_IRDY#

H19,

PSTS

Secondary IRDY (Active LOW). Driven by the

initiator of a transaction to indicate its ability to

complete current data phase on the secondary side.

Once asserted in a data phase, it is not de-asserted until

the end of the data phase. Before tri-stated, it is driven

to a de-asserted state for one cycle.

S1_TRDY#,

S2_TRDY#

H18,

PSTS

Secondary TRDY (Active LOW). Driven by the

target of a transaction to indicate its ability to complete

current data phase on the secondary side. Once

asserted in a data phase, it is not de-asserted until the

end of the data phase. Before tri-stated, it is driven to a

de-asserted state for one cycle.

S1_DEVSEL#,

S2_DEVSEL#

J20,

PSTS

Secondary Device Select (Active LOW). Asserted by

the target indicating that the device is accepting the

transaction. As a master, PI7C7300D waits for the

assertion of this signal within 5 cycles of S1_FRAME#

or S2_FRAME# assertion; otherwise, terminate with

master abort. Before tri-stated, it is driven to a de-

asserted state for one cycle.

S1_STOP#,

S2_STOP#

J19,

PSTS

Secondary STOP (Active LOW). Asserted by the

target indicating that the target is requesting the

initiator to stop the current transaction. Before tri-

stated, it is driven to a de-asserted state for one cycle.

S1_LOCK#,

S2_LOCK#

J18,

PSTS

Secondary LOCK (Active LOW). Asserted by the

master for multiple transactions to complete.

S1_PERR#,

S2_PERR#

J17,

PSTS

Secondary Parity Error (Active LOW). Asserted

when a data parity error is detected for data received on

the secondary interface. Before being tri-stated, it is

driven to a de-asserted state for one cycle.

S1_SERR#,

S2_SERR#

K20,

Secondary System Error (Active LOW). Can be

driven LOW by any device to indicate a system error

condition.

S1_REQ#[7:0],

S2_REQ#[6:0]

B11, A12, D13,

C13, C15, A16,

C17, B17

R3, P2, P1, M2,

M1, K1, K3

PIU

Secondary Request (Active LOW). This is asserted

by an external device to indicate that it wants to start a

transaction on the secondary bus. The input is

externally pulled up through a resistor to VDD.

S1_GNT#[7:0]

S2_GNT#[6:0]

C11, B12, B13,

A14, D14, B16,

D16, B18

P4, R1, N4, M3,

L4, L1, K2

Secondary Grant (Active LOW). PI7C7300D asserts

this pin to access the secondary bus. PI7C7300D de-

asserts this pin for at least 2 PCI clock cycles before

asserting it again. During idle and S1_GNT# or S2-

GNT# asserted, PI7C7300D will drive S1_AD,

S1_CBE, and S1_PAR or S2_AD, S2_CBE, and

S2_PAR.

S1_RESET#,

S2_RESET#

B10,

Secondary RESET (Active LOW). Asserted when

any of the following conditions are met:

Signal P_RESET# is asserted.

Secondary reset bit in bridge control register in

configuration space is set.

When asserted, all control signals are tri-stated and

zeroes are driven on S1_AD, S1_CBE, and S1_PAR or

S2_AD, S2_CBE, and S2_PAR.

S1_EN,

S2_EN

W3,

PIU

Secondary Enable (Active HIGH). When S1_EN or

S2_EN is inactive, secondary bus PCI S1 or PCI S2

will be asynchronously tri-stated.

S1_M66EN,

S2_M66EN

D7,

Secondary Interface 66MHz Operation. This input

is used to specify if PI7C7300D is capable of running

at 66MHz on the secondary side. When HIGH, the S1

or S2 bus may run at 66MHz. When LOW, the S1 or

S2 bus may only run at 33MHz.

If P_M66EN is pulled LOW, both S1_M66EN and

S2_M66EN need to be LOW.

PI7C7300D Datasheet(PDF) 16 Page - Pericom Semiconductor Corporation

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