PI7C7300D datasheet(68/107 Pages) PERICOM

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PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

the masters in the following fashion (high priority members are given in italics, low

priority members, in boldface type): B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1,

m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7 and so on.

Figure 9-1 SECONDARY ARBITER EXAMPLE

Each bus master, including PI7C7300D, can be configured to be in either the low priority

group or the high priority group by setting the corresponding priority bit in the arbiter-

control register. The arbiter-control register is located at offset 40h. Each master has a

corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If

the bit is set to 0, the master is assigned to the low priority group. If all the masters are

assigned to one group, the algorithm defaults to a straight rotating priority among all the

masters. After reset, all external masters are assigned to the low priority group, and

PI7C7300D is assigned to the high priority group. PI7C7300D receives highest priority

on the target bus every other transaction, and priority rotates evenly among the other

masters.

Priorities are re-evaluated every time S1_FRAME# or S2_FRAME# is asserted at the

start of each new transaction on the secondary PCI bus. From this point until the time

that the next transaction starts, the arbiter asserts the grant signal corresponding to the

highest priority request that is asserted. If a grant for a particular request is asserted, and

a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant

signal and asserts the grant corresponding to the new higher priority request on the next

PCI clock cycle. When priorities are re-evaluated, the highest priority is assigned to the

next highest priority master relative to the master that initiated the previous transaction.

The master that initiated the last transaction now has the lowest priority in its group.

If PI7C7300D detects that an initiator has failed to assert S1_FRAME# or S2_FRAME#

after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-

asserts the grant. That master does not receive any more grants until it deasserts its

request for at least one PCI clock cycle.

To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one

grant signal in the same PCI cycle in which it deasserts another. It de-asserts one grant

and asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI

bus is busy, that is, either S1_FRAME# (S2_FRAME#) or S1_IRDY# (S2_IRDY#) is

asserted, the arbiter can de-assert one grant and assert another grant during the same PCI

clock cycle.

Page 68 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

PI7C7300D Datasheet(PDF) 68 Page - Pericom Semiconductor Corporation