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PI7C7300D Datasheet(PDF) 59 Page - Pericom Semiconductor Corporation |
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PI7C7300D Datasheet(HTML) 59 Page - Pericom Semiconductor Corporation |
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59 / 107 page  PI7C7300D 3-PORT PCI-TO-PCI BRIDGE Page 59 of 107 Pericom Semiconductor November 2005 - Revision 1.01 Table 7-3 shows setting data parity detected bit in the primary interface’s status register. This bit is set under the following conditions: PI7C7300D must be a master on the primary bus. The parity error response bit in the command register, corresponding to the primary interface, must be set. The P_PERR# signal is detected asserted or a parity error is detected on the primary bus. Table 7-3 SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT Primary Data Parity Bit Transaction Type Direction Bus Where Error Was Detected Primary / Secondary Parity Error Response Bits 0 Read Downstream Primary x / x 0 Read Downstream Secondary x / x 1 Read Upstream Primary 1 / x 0 Read Upstream Secondary x / x 0 Posted Write Downstream Primary x / x 0 Posted Write Downstream Secondary x / x 1 Posted Write Upstream Primary 1 / x 0 Posted Write Upstream Secondary x / x 0 Delayed Write Downstream Primary x / x 0 Delayed Write Downstream Secondary x / x 1 Delayed Write Upstream Primary 1 / x 0 Delayed Write Upstream Secondary x / x X = don’t care Table 7-4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: The PI7C7300D must be a master on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus. Table 7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED BIT Secondary Detected Parity Detected Bit Transaction Type Direction Bus Where Error Was Detected Primary / Secondary Parity Error Response Bits 0 Read Downstream Primary x / x 1 Read Downstream Secondary x / 1 0 Read Upstream Primary x / x 0 Read Upstream Secondary x / x 0 Posted Write Downstream Primary x / x 1 Posted Write Downstream Secondary x / 1 0 Posted Write Upstream Primary x / x 0 Posted Write Upstream Secondary x / x 0 Delayed Write Downstream Primary x / x 1 Delayed Write Downstream Secondary x / 1 0 Delayed Write Upstream Primary x / x 0 Delayed Write Upstream Secondary x / x X= don’t care |
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