MB9B320TA datasheet(118/141 Pages) SPANSION

118 / 141 page

D a t a S h e e t

January 30, 2015, MB9B320TA_DS706-00062-2v0-E

115

CONFIDENTIAL

12-bit A/D Converter

・Electrical characteristics for the A/D converter

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)

Parameter

Symbol

name

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Integral Nonlinearity

± 1.5

± 4.5

LSB

AVRH = 2.7V

to 5.5V

Differential Nonlinearity

± 2.2

± 2.5

LSB

Zero transition voltage

VZT

ANxx

± 6

± 15

Full-scale transition

voltage

VFST

ANxx

AVRH ± 5 AVRH ± 15

Conversion time

1.0*

μs

Sampling time*

0.3

μs

Compare clock cycle*

Tcck

1000

State transition time to

operation permission

Tstt

1.0

μs

Analog input capacity

CAIN

9.5

Analog input resistor

RAIN

1.62

kΩ

AVCC ≥ 4.5V

2.35

AVCC < 4.5V

Interchannel disparity

LSB

Analog port input current

ANxx

μA

Analog input voltage

ANxx

AVRL

AVRH

Reference voltage

AVRH

2.7

AVCC

AVRL

AVSS

*1 : The conversion time is the value of sampling time (Ts) + compare time (Tc).

The condition of the minimum conversion time is when the value of sampling time: 300ns, the value of

compare time:700ns (AVCC ≥ 4.5V).

Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).

For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3

Family PERIPHERAL MANUAL Analog Macro Part".

The register setting of the A/D Converter are reflected in the operation according to the APB bus clock

timing.

The sampling clock and compare clock is generated from the Base clock (HCLK).

About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data

sheet.

*2 : A necessary sampling time changes by external impedance.

Ensure that it sets the sampling time to satisfy (Equation 1).

*3 : The compare time (Tc) is the value of (Equation 2).

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