ADIS16445

Data Sheet

Rev. F | Page 4 of 22

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

2.4

V

0.4

V

FLASH MEMORY

10,000

Cycles

20

Years

Time until new data is available

Power-On Start-Up Time

175

ms

55

ms

Flash Memory Back-Up Time

55

ms

Flash Memory Test Time

20

ms

Automatic Self-Test Time

SMPL_PRD = 0x0001

16

ms

CONVERSION RATE

xGYRO_OUT, xACCL_OUT

SMPL_PRD = 0x0001

819.2

SPS

Clock Accuracy

±3

%

0.8

1.1

kHz

POWER SUPPLY

Operating voltage range, VDD

3.15

3.3

3.45

V

Power Supply Current

VDD = 3.15 V

74

mA

1

The repeatability specifications represent analytical projections, which are based off of the following drift contributions and conditions: temperature hysteresis (−40°C

to +85°C), electronics drift (high-temperature operating life test: 85°C, 500 hours), drift from temperature cycling (JESD22, Method A104-C, Method N, 500 cycles,

−40°C to +85°C), rate random walk (10 year projection), and broadband noise.

2

Bias repeatability describes a long-term behavior, over a variety of conditions. Short-term repeatability is related to the in-run bias stability and noise density specifications.

3

The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant.

4

Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C.

5

temperature.

6

These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may affect overall accuracy.

7

The RST line must be held low for at least 10 μs to assure a proper reset and recovery sequence.

8

The sync input clock functions below the specified minimum value but at reduced performance levels.