ADIS16445

Data Sheet

Rev. F | Page 10 of 22

USER INTERFACE

The ADIS16445 is an autonomous system that requires no user

initialization. When it has a valid power supply, it initializes itself

and starts sampling, processing, and loading sensor data into

the output registers at a sample rate of 819.2 SPS. DIO1 pulses

high after each sample cycle concludes. The SPI interface enables

simple integration with many embedded processor platforms,

as shown in Figure 9 (electrical connection) and Table 7 (pin

functions).

SYSTEM

PROCESSOR

SPI MASTER

ADIS16445

SCLK

CS

DIN

DOUT

SCLK

SS

MOSI

MISO

+3.3V

IRQ

DIO1

VDD

I/O LINES ARE COMPATIBLE WITH

3.3V LOGIC LEVELS

10

6

3

5

4

7

11

12

13

14

15

Figure 9. Electrical Connection Diagram

Table 7. Generic Master Processor Pin Names and Functions

Pin Name

Function

SS

Slave select

SCLK

Serial clock

MOSI

Master output, slave input

MISO

Master input, slave output

IRQ

Interrupt request

The ADIS16445 SPI interface supports full duplex serial commu-

nication (simultaneous transmit and receive) and uses the bit

sequence shown in Figure 12. Table 8 provides a list of the most

common settings that require attention to initialize the serial

port of a processor for the ADIS16445 SPI interface.

Table 8. Generic Master Processor SPI Settings

Processor Setting

Description

Master

The ADIS16445 operates as a slave

Maximum serial clock rate

SPI Mode 3

CPOL = 1 (polarity), CPHA = 1 (phase)

MSB-First Mode

Bit sequence

16-Bit Mode

Shift register/data length

1

For burst read, SCLK rate ≤ 1 MHz.

READING SENSOR DATA

The ADIS16445 provides two different options for acquiring

sensor data: a single register and a burst register. A single regis-

ter read requires two 16-bit SPI cycles. The first cycle requests

the contents of a register using the bit assignments in Figure 12.

Bit DC7 to Bit DC0 are don’t cares for a read, and then the output

register contents follow on DOUT during the second sequence.

Figure 10 includes three single register reads in succession.

In this example, the process starts with DIN = 0x0400 to request

the contents of XGYRO_OUT, then follows with 0x0600 to re-

quest YGYRO_OUT, and 0x0800 to request ZGYRO_OUT. Full

duplex operation enables processors to use the same 16-bit SPI

cycle to read data from DOUT while requesting the next set of

data on DIN. Figure 11 provides an example of the four SPI

signals when reading XGYRO_OUT in a repeating pattern.

XGYRO_OUT

DIN

DOUT

YGYRO_OUT

ZGYRO_OUT

0x0400

0x0600

0x0800

Figure 10. SPI Read Example

SCLK

CS

DIN

DOUT

DOUT = 1111 10011101 1010 = 0xF9DA = –15.74°/sec LSBs ≥ –62.96°/sec

DIN = 0000 0100 0000 0000 = 0x0400

Figure 11. Example SPI Read, Second Sequence, SENS_AVG[15:8] = 0x04

R/W

R/W

A6

A5

A4

A3

A2

A1

A0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

CS

SCLK

DIN

DOUT

A6

A5

D13

D14

D15

NOTES

1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]

IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0.

2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.

Figure 12. SPI Communication Bit Sequence