ADIS16445SLASHPCBZ datasheet(11/22 Pages) AD

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Data Sheet

ADIS16445

Rev. F | Page 11 of 22

Burst Read Function

The burst read function provides a way to read all of the data in

one continuous stream of bits, with no stall time. As shown in

Figure 13, start this mode by setting DIN = 0x3E00 while keeping

CS low for eight additional 16-bit read cycles. These eight cycles

produce the following sequence of output registers on DOUT:

DIAG_STAT, XGYRO_OUT, YGYRO_OUT, ZGYRO_OUT,

XACCL_OUT, YACCL_OUT, ZACCL_OUT, and TEMP_OUT.

GLOB_CMD

SCLK

DIN

DOUT

XGYRO_OUT

DIAG_STAT

TEMP_OUT

Figure 13. Burst Read Sequence

SPI Read Test Sequence

Figure 14 provides a test pattern for testing the SPI communica-

tion. In this pattern, write 0x5600 to the DIN line in a repeating

pattern and raise chip select for at least 9 µs between each 16-bit

sequence. Starting with the second 16-bit sequence, DOUT

produces the contents of the PROD_ID register, 0x403D (see

Table 22).

DOUT = 0100 0000 0011 1101 = 0x403D = 16,445

DIN = 0101 0110 0000 0000 = 0x5600

SCLK

DIN

DOUT

Figure 14. SPI Test Read Pattern DIN = 0x5600, DOUT = 0x403D

DEVICE CONFIGURATION

The control registers in Table 6 provide users with a variety of

configuration options. The SPI provides access to these registers,

one byte at a time, using the bit assignments in Figure 12. Each

and Bits[15:8] represent the upper address. Figure 15 provides

an example of writing 0x04 to Address 0x37 (SMPL_PRD[15:8],

using DIN = 0xB704). This example reduces the sample rate by

a factor of eight (see Table 28).

SCLK

DIN

DIN = 1011 0111 0000 0100 = 0xB704, WRITES 0x04 TO ADDRESS 0x37.

Figure 15. Example SPI Write Sequence

Dual Memory Structure

Writing configuration data to a control register updates its SRAM

contents, which are volatile. After optimizing each relevant control

0xBE08) to back up these settings in nonvolatile flash memory.

The flash backup process requires a valid power supply level for

the entire process time, 75 ms. Table 6 provides a user register

memory map that includes a flash backup column. A Yes in this

column indicates that a register has a mirror location in flash

and, when backed up properly, it automatically restores itself

during startup or after a reset. Figure 16 provides a diagram of

the dual memory structure used to manage operation and store

critical user settings.

NONVOLATILE

FLASH MEMORY

(NO SPI ACCESS)

MANUAL

FLASH

BACKUP

START-UP

RESET

VOLATILE

SRAM

SPI ACCESS

Figure 16. SRAM and Flash Memory Diagram

ADIS16445/PCBZ Datasheet(PDF) 11 Page - Analog Devices

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