RT7304 datasheet(4/14 Pages) RICHTEK

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RT7304

DS7304-04 February 2015

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Protections

LED Open-Circuit Protection

In an event of output open circuit, the converter will be

shut down to prevent being damaged, and it will be auto-

restarted when the output is recovered. Once the LED is

open, the output voltage and VZCD will rise. When the

sample-and-hold ZCD voltage (VZCD_SH) exceeds its OV

threshold (VZCD_OVP, 3.1V typ.), output OVP will be

activated and the PWM output (GD pin) will be forced low

to turn off the main switch. If the output is still open-circuit

when the converter restarts, the converter will be shut

down again.

Figure 4. Valley Signal Generating Method

Figure 5 illustrates how valley signal triggers PWM. If no

valley signal is detected for a long time, the next PWM is

triggered by a starter circuit at the end of the interval (tSTART,

130

μs typ.) which starts at the rising edge of the previous

PWM signal. A blanking time (tS(MIN), 8.5

μs typ.), which

starts at the rising edge of the previous PWM signal, limits

minimum switching period. When the tS(MIN) interval is

on-going, all of valley signals are not allowed to trigger

the next PWM signal. After the end of the tS(MIN) interval,

the coming valley will trigger the next PWM signal. If one

or more valley signals are detected during the tS(MIN)

interval and no valley is detected after the end of the tS(MIN)

interval, the next PWM signal will be triggered

automatically at the end of the tS(MIN) + 5

μs (typ.).

Figure 5. PWM Triggered Method

VZCD

Valley

Signal

PWM

500ns

tMASK

VZCDA

VZCDT

PWM

tS(MIN)

5µs

Valley

Signal

PWM

tS(MIN)

Valley

Signal

PWM

Valley

Signal

tS(MIN)

PWM

Valley

Signal

tSTART

……

Quasi-Resonant Operation

For improving converter's efficiency, the RT7304 detects

valleys of the Drain-to-Source voltage (VDS) of main switch

and turns on it near the selected valley. For the valley

detections, a pulse of the “valley signal” is generated

after a 500ns(typ.) delay time which starts at which the

voltage (VZCD) on ZCD pin goes down and reaches the

voltage threshold (VZCDT, 0.4V typ.). During the rising of

the VZCD, the VZCD must reach the voltage threshold

(VZCDA, 0.5V typ.). Otherwise, no pulse of the “valley

signal” is generated. Moreover, if the timing when the

falling VZCD reaches VZCDT is not later than a mask time

(tMASK, 2

μs typ.) then the valley signal will be masked and

regards as no valley, as shown in Figure 4.

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