CS5530 datasheet(60/241 Pages) NSC

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Revision 4.1

Functional Description (Continued)

3.4.3

Peripheral Power Management

The CS5530 provides peripheral power management

using a combination of device idle timers, address traps,

and general purpose I/O pins. Idle timers are used in con-

junction with traps to support powering down peripheral

devices. Eight programmable GPIO (general purpose I/O)

pins are included for external device power control as well

as other functions. All I/O addresses are decoded in 16

bits. All memory addresses are decoded in 32 bits.

3.4.3.1

Device Idle Timers and Traps

Idle timers are used to power manage a peripheral by

determining when the peripheral has been inactive for a

specified period of time, and removing power from the

peripheral at the end of that time period.

Idle timers are provided for the commonly-used peripher-

als (FDC, IDE, parallel/serial ports, and mouse/keyboard).

In addition, there are three user-defined timers that can

be configured for either I/O or memory ranges.

Theidletimersare 16-bit countdowntimerswitha1sec-

ond time base, providing a time-out range of 1 to 65536

seconds (1092 minutes) (18 hours).

When the idle timer count registers are loaded with a non-

zero value and enabled, the timers decrement until one of

two possibilities happens: a bus cycle occurs at that I/O or

memory range, or the timer decrements to zero.

If a bus cycle occurs, the timer is reloaded and begins

decrementing again. If the timer decrements to zero, and

power management is enabled (F0 Index 80h[0] = 1), the

timer generates an SMI.

When an idle timer generates an SMI, the SMI handler

manages the peripheral power, disables the timer, and

enables the trap. The next time an event occurs, the trap

generates an SMI. This time, the SMI handler applies

power to the peripheral, resets the timer, and disables the

trap.

Tables 3-16 through3-24show thedeviceassociatedidle

timers and traps programming bits.

Table 3-16. Power Management Global Enabling Bits

Bit

Description

F0 Index 80h

Power Management Enable Register 1 (R/W)

Reset Value = 00h

Traps: Globally enable all power management device I/O traps: 0 = Disable; 1 = Enable.

This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h.

Idle Timers: Globally enable all power management device idle timers: 0 = Disable; 1 = Enable.

Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts.

This bit has no affect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h).

Power Management: Global power management: 0 = Disable; 1 = Enabled.

This bit must be set (1) immediately after POST for power management resources to function.

CS5530 Datasheet(PDF) 60 Page - National Semiconductor (TI)

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