CS5530 datasheet(99/241 Pages) NSC

99 / 241 page

Revision 4.1

www.national.com

Functional Description (Continued)

Table 3-46. Interrupt Edge/Level Select Registers

Bit

Description

I/O Port 4D0h

Interrupt Edge/Level Select Register 1 (R/W)

Reset Value = 00h

IRQ7 Edge or Level Select: Selects PIC IRQ7 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

IRQ6 Edge or Level Select: Selects PIC IRQ6 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

IRQ5 Edge or Level Select: Selects PIC IRQ5 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

IRQ4 Edge or Level Select: Selects PIC IRQ4 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

IRQ3 Edge or Level Select: Selects PIC IRQ3 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

Reserved: Set to 0.

IRQ1 Edge or Level Select: Selects PIC IRQ1 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

Reserved: Set to 0.

Notes:

If ICW1 - bit 3 in the PIC is set as level, it overrides this setting.

This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared).

I/O Port 4D1h

Interrupt Edge/Level Select Register 2 (R/W)

Reset Value = 00h

IRQ15 Edge or Level Select: Selects PIC IRQ15 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

IRQ14 Edge or Level Select: Selects PIC IRQ14 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

Reserved: Set to 0.

IRQ12 Edge or Level Select: Selects PIC IRQ12 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

IRQ11 Edge or Level Select: Selects PIC IRQ11 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

IRQ10 Edge or Level Select: Selects PIC IRQ10 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

IRQ9 Edge or Level Select: Selects PIC IRQ9 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2)

Reserved: Set to 0.

Notes:

If ICW1 - bit 3 in the PIC is set as level, it overrides this setting.

This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared).

CS5530 Datasheet(PDF) 99 Page - National Semiconductor (TI)