CS5530 datasheet(67/241 Pages) NSC

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Functional Description (Continued)

Table 3-23. User Defined Device 2 (UDEF2) Idle Timer and Trap Related Registers

Bit

Description

F0 Index 81h

Power Management Enable Register 4 (R/W)

Reset Value = 00h

User Defined Device 2 (UDEF2) Idle Timer Enable: Turn on UDEF2 Idle Timer Count Register (F0 Index A2h) and gen-

erate an SMI when the timer expires: 0 = Disable; 1 = Enable.

If an access occurs in the programmed address range the timer is reloaded with the programmed count.

UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[5].

F0 Index 82h

Power Management Enable Register 3 (R/W)

Reset Value = 00h

User Defined Device 2 (UDEF2) Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF2 address pro-

gramming is at F0 Index C4h (base address register) and CDh (control register).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].

Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[3].

F0 Index A2h-A3h

User Defined Device 2 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 2 (UDEF2) Idle Timer Count: This idle timer determines when the device configured as UDEF2 is

not in use so that it can be power managed. The 16-bit value programmed here represents the period of inactivity for this

device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an

access occurs to memory or I/O address space configured in the F0 Index C4h (base address register) and F0 Index CDh

(control register). The counter uses a 1 second timebase.

To enable this timer set F0 Index 81h[5] = 1.

Top level SMI status reporting is at F1BAR+Memory Offset 00h/02h[0] and secondary level SMI status reporting is at F0

Index 85h/F5h[5].

F0 Index C4h-C7h

User Defined Device 2 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 2 (UDEF2) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar-

ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh).

F0 Index CDh

User Defined Device 2 Control Register (R/W)

Reset Value = 00h

Memory or I/O Mapped: User Defined Device 2 is: 0 = I/O; 1 = Memory.

6:0

Mask:

If bit 7 = 0 (I/O):

Bit 6

0 = Disable write cycle tracking

1 = Enable write cycle tracking

Bit 5

0 = Disable read cycle tracking

1 = Enable read cycle tracking

Bits 4:0

Mask for address bits A[4:0]

If bit 7 = 1 (M/IO):

Bits 6:0

Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored.

Note: A "1" in a mask bit means that the address bit is ignored for comparison.

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