COP8CDR9KMT7 datasheet(23/84 Pages) NSC

23 / 84 page

10.0 Functional Description

(Continued)

The format of the Option register is as follows:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SECURITY

Reserved

WATCH

DOG

HALT

FLEX

Bits 7, 6 These bits are reserved and must be 0.

Bit 5

= 1

Security enabled. Flash Memory read and write

are not allowed except in User ISP/Virtual E

2 com-

mands. Mass Erase is allowed.

= 0

Security disabled. Flash Memory read and write

are allowed.

Bits 4, 3 These bits are reserved and must be 0.

Bit 2

= 1

WATCHDOG feature disabled. G1 is a general

purpose I/O.

= 0

WATCHDOG

feature

enabled.

WATCHDOG output with weak pullup.

Bit 1

= 1

HALT mode disabled.

= 0

HALT mode enabled.

Bit 0

= 1

Execution following RESET will be from Flash

Memory.

= 0

Flash Memory is erased. Execution following RE-

SET will be from Boot ROM with the MICROWIRE/

PLUS ISP routines.

The COP8 assembler defines a special ROM section type,

CONF, into which the Option Register data may be coded.

The Option Register is programmed automatically by pro-

grammers that are certified by National.

The user needs to ensure that the FLEX bit will be set when

the device is programmed.

The following examples illustrate the declaration of the Op-

tion Register.

Syntax:

[label:].sect

config, conf

.db

value

;1 byte,

;configures

;options

.endsect

Example: The following sets a value in the Option Register

and User Identification for a COP8CBR9HVA7. The Option

WATCHDOG enabled HALT mode enabled and execution

will commence from Flash Memory.

.chip

8CBR

.sect

option, conf

.db

0x01

;wd, halt, flex

.endsect

...

.end

start

Note: All programmers certified for programming this family

of parts will support programming of the Option Register.

Please contact National or your device programmer supplier

for more information.

10.6 SECURITY

The device has a security feature which, when enabled,

prevents external reading of the Flash program memory. The

security bit in the Option Register determines, whether se-

curity is enabled or disabled. If the security feature is dis-

abled, the contents of the internal Flash Memory may be

read

external

programmers

the

built

MICROWIRE/PLUS serial interface ISP. Security must be

enforced by the user when the contents of the Flash

Memory are accessed via the user ISP or Virtual EE-

PROM capability.

If the security feature is enabled, then any attempt to exter-

nally read the contents of the Flash Memory will result in the

value FF (hex) being read from all program locations (except

the Option Register). In addition, with the security feature

enabled, the write operation to the Flash program memory

and Option Register is inhibited. Page Erases are also inhib-

ited when the security feature is enabled. The Option Reg-

ister is readable regardless of the state of the security bit by

accessing location FFFF (hex). Mass Erase Operations are

possible regardless of the state of the security bit.

The security bit can be erased only by a Mass Erase of the

entire contents of the Flash unless Flash operation is under

the control of User ISP functions.

Note: The actual memory address of the Option Register is

7FFF (hex), however the MICROWIRE/PLUS ISP routines

require the address FFFF (hex) to be used to read the

Option Register when the Flash Memory is secured.

The entire Option Register must be programmed at one time

and cannot be rewritten without first erasing the entire last

page of Flash Memory.

10.7 RESET

The device is initialized when the RESET pin is pulled low or

the On-chip Brownout Reset is activated. The Brownout

Reset feature is not available on the COP8CDR9.

The following occurs upon initialization:

Port A: TRI-STATE (High Impedance Input)

Port B: TRI-STATE (High Impedance Input)

Port C: TRI-STATE (High Impedance Input)

Port D: HIGH

Port E: TRI-STATE (High Impedance Input)

Port F: TRI-STATE (High Impedance Input)

Port G: TRI-STATE (High Impedance Input). Exceptions: If

Watchdog is enabled, then G1 is Watchdog output. G0

and G2 have their weak pull-up enabled during RESET.

Port L: TRI-STATE (High Impedance Input)

PC: CLEARED to 0000

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

10137411

FIGURE 8. Reset Logic

COP8CDR9KMT7 Datasheet(PDF) 23 Page - National Semiconductor (TI)

COP8CDR9KMT7 Datasheet(HTML) 23 Page - National Semiconductor (TI)

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