COP8CDR9KMT7 datasheet(24/84 Pages) NSC

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10.0 Functional Description

(Continued)

T2CNTRL: CLEARED

T3CNTRL: CLEARED

HSTCR: CLEARED

ITMR: Cleared except Bit 6 (HSON) = 1

Accumulator, Timer 1, Timer 2 and Timer 3:

RANDOM after RESET

WKEN, WKEDG: CLEARED

WKPND: RANDOM

SP (Stack Pointer):

Initialized to RAM address 06F Hex

B and X Pointers:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

S Register: CLEARED

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

USART:

PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit

which is set to one.

ANALOG TO DIGITAL CONVERTER:

ENAD: CLEARED

ADRSTH: RANDOM

ADRSTL: RANDOM

ISP CONTROL:

ISPADLO: CLEARED

ISPADHI: CLEARED

PGMTIM: PRESET TO VALUE FOR 10 MHz CKI

WATCHDOG (if enabled):

The device comes out of reset with both the WATCHDOG

logic and the Clock Monitor detector armed, with the

WATCHDOG service window bits set and the Clock Moni-

tor bit set. The WATCHDOG and Clock Monitor circuits

are inhibited during reset. The WATCHDOG service win-

dow bits being initialized high default to the maximum

WATCHDOG service window of 64k T0 clock cycles. The

Clock Monitor bit being initialized high will cause a Clock

Monitor error following reset if the clock has not reached

the minimum specified frequency at the termination of

reset. A Clock Monitor error will cause an active low error

output on pin G1. This error output will continue until

16–32 T0 clock cycles following the clock frequency

reaching the minimum specified value, at which time the

G1 output will go high.

10.7.1 External Reset

The RESET input when pulled low initializes the device. The

RESET pin must be held low for a minimum of one instruc-

tion cycle to guarantee a valid reset. During Power-Up ini-

tialization, the user must ensure that the RESET pin of a

device without the Brownout Reset feature is held low until

the device is within the specified V

CC voltage. Any rising

edge on the RESET pin while V

CC is below the specified

operating range may cause unpredictable results. An R/C

circuit on the RESET pin with a delay 5 times (5x) greater

than the power supply rise time is recommended. Reset

should also be wide enough to ensure crystal start-up upon

Power-Up.

RESET may also be used to cause an exit from the HALT

mode.

A recommended reset circuit for this device is shown in

Figure 9.

10.7.2 On-Chip Brownout Reset

When enabled, the device generates an internal reset as

CC rises. While VCC is less than the specified brownout

voltage (V

bor), the device is held in the reset condition and

the Idle Timer is preset with 00Fx (240–256 t

C). When VCC

reaches a value greater than V

bor, the Idle Timer starts

counting down. Upon underflow of the Idle Timer, the internal

reset is released and the device will start executing instruc-

tions. This internal reset will perform the same functions as

external reset. Once V

CC is above the Vbor and this initial Idle

Timer time-out takes place, instruction execution begins and

the Idle Timer can be used normally. If, however, V

CC drops

below the selected V

bor, an internal reset is generated, and

the Idle Timer is preset with 00Fx. The device now waits until

CC is greater than Vbor and the countdown starts over.

When enabled, the functional operation of the device, at

frequency, is guaranteed down to the V

bor level.

10137412

FIGURE 9. Reset Circuit Using External Reset

COP8CDR9KMT7 Datasheet(PDF) 24 Page - National Semiconductor (TI)

COP8CDR9KMT7 Datasheet(HTML) 24 Page - National Semiconductor (TI)

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