COP8CDR9KMT7 datasheet(55/84 Pages) NSC

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15.0 A/D Converter (Continued)

15.2 A/D OPERATION

The A/D conversion is completed within fifteen A/D converter

clocks. The A/D Converter interface works as follows. Setting

the ADBSY bit in the A/D control register ENAD initiates an

A/D conversion. The conversion sequence starts at the be-

ginning of the write to ENAD operation which sets ADBSY,

thus powering up the A/D. At the first edge of the Converter

clock following the write operation, the sample signal turns

on for three clock cycles. At the end of the conversion, the

internal conversion complete signal will clear the ADBSY bit

and power down the A/D. The A/D 10-bit result is immedi-

ately loaded into the A/D result registers (ADRSTH and

ADRSTL) upon completion.

Inadvertent changes to the ENAD register during conversion

are prevented by the control logic of the A/D. Any attempt to

write any bit of the ENAD Register except ADBSY, while

ADBSY is a one, is ignored. ADBSY must be cleared either

by completion of an A/D conversion or by the user before the

prescaler, conversion mode or channel select values can be

changed. After stopping the current conversion, the user can

load different values for the prescaler, conversion mode or

channel select and start a new conversion in one instruction.

15.2.1 Prescaler

The A/D Converter (A/D) contains a prescaler option that

allows two different clock speed selections as shown in

Table 23. The A/D clock frequency is equal to MCLK divided

by the prescaler value. Note that the prescaler value must be

chosen such that the A/D clock falls within the specified

range. The maximum A/D frequency is 1.25 MHz. This

equates to a 800 ns A/D clock cycle.

The A/D Converter takes 15 A/D clock cycles to complete a

conversion. Thus the minimum A/D conversion time is 12.0

µs when a prescaler of 16 has been selected with

MCLK = 20 MHz. The 15 A/D clock cycles needed for

conversion consist of 3 cycles for sampling, 1 cycle for

auto-zeroing the comparator, 10 cycles for converting, 1

cycle for loading the result into the result registers, for stop-

ping and for re-initializing. The ADBSY flag provides an A/D

clock inhibit function, which saves power by powering down

the A/D when it is not in use.

Note: The A/D Converter is also powered down when the

device is in either the HALT or IDLE modes. If the A/D is

running when the device enters the HALT or IDLE modes,

the A/D powers down and then restarts the conversion from

the beginning with a corrupted sampled voltage (and thus an

invalid result) when the device comes out of the HALT or

IDLE modes.

15.3 ANALOG INPUT AND SOURCE RESISTANCE

CONSIDERATIONS

Figure 28 shows the A/D pin model in single ended mode.

The differential mode has a similar A/D pin model. The leads

to the analog inputs should be kept as short as possible.

Both noise and digital clock coupling to an A/D input can

cause conversion errors. The clock lead should be kept

away from the analog input line to reduce coupling.

Source impedances greater than 3 k

Ω on the analog input

lines will adversely affect the internal RC charging time

during input sampling. As shown in Figure 28, the analog

switch to the DAC array is closed only during the 3 A/D cycle

sample time. Large source impedances on the analog inputs

may result in the DAC array not being charged to the correct

voltage levels, causing scale errors.

If large source resistance is necessary, the recommended

solution is to slow down the A/D clock speed in proportion to

the source resistance. The A/D Converter may be operated

at the maximum speed for R

S less than 3 k

Ω. For R

S greater

than 3 k

Ω, A/D clock speed needs to be reduced. For ex-

ample, with R

S =6k

Ω, the A/D Converter may be operated

at half the maximum speed. A/D Converter clock speed may

be slowed down by either increasing the A/D prescaler

divide-by or decreasing the CKI clock frequency. The A/D

minimum clock speed is 65.536 kHz.

10137453

*The analog switch is closed only during the sample time.

FIGURE 28. A/D Pin Model (Single Ended Mode)

COP8CDR9KMT7 Datasheet(PDF) 55 Page - National Semiconductor (TI)

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