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COP8CDR9KMT7 Datasheet(PDF) 27 Page - National Semiconductor (TI) |
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COP8CDR9KMT7 Datasheet(HTML) 27 Page - National Semiconductor (TI) |
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27 / 84 page  10.0 Functional Description (Continued) 10.8.2 Clock Doubler This device contains a frequency doubler that doubles the frequency of the oscillator selected to operate the main microcontroller core. The details of how to select either the high speed oscillator or low speed oscillator are described in, Power Saving Features. When the high speed oscillator connected to CKI operates at 10 MHz, the internal clock frequency is 20 MHz, resulting in an instruction cycle time of 0.5 µs. When the 32 kHz oscillator connected to L0 and L1 is selected, the internal clock frequency is 64 kHz, resulting in an instruction cycle of 152.6 µs. The output of the clock doubler is called MCLK and is referenced in many places within this document. 10.9 CONTROL REGISTERS 10.9.1 CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0 Bit 7 Bit 0 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C1 Timer T1 mode control bit T1C0 Timer T1 Start/Stop control in timer modes 1 and 2. T1 Underflow Interrupt Pending Flag in timer mode 3 MSEL Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively IEDG External interrupt edge polarity select (0 = Rising edge, 1 = Falling edge) SL1 & SL0 Select the MICROWIRE/PLUS clock divide by (00 = 2, 01 = 4, 1x = 8) 10.9.2 PSW Register (Address X'00EF) HC C T1PNDA T1ENA EXPND BUSY EXEN GIE Bit 7 Bit 0 The PSW register contains the following select bits: HC Half Carry Flag C Carry Flag T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3) T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN Enable external interrupt GIE Global interrupt enable (enables interrupts) The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags. 10.9.3 ICNTRL Register (Address X'00E8) Unused LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB Bit 7 Bit 0 The ICNTRL register contains the following bits: LPEN L Port Interrupt Enable (Multi-Input Wake-up/Interrupt) T0PND Timer T0 Interrupt pending T0EN Timer T0 Interrupt Enable (Bit 12 toggle) µWPND MICROWIRE/PLUS interrupt pending µWEN Enable MICROWIRE/PLUS interrupt T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge T1ENB Timer T1 Interrupt Enable for T1B Input capture edge 10.9.4 T2CNTRL Register (Address X'00C6) T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB Bit 7 Bit 0 The T2CNTRL register contains the following bits: T2C3 Timer T2 mode control bit T2C2 Timer T2 mode control bit T2C1 Timer T2 mode control bit T2C0 Timer T2 Start/Stop control in timer modes 1 and 2, Timer T2 Underflow Interrupt Pending Flag in timer mode 3 T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3) T2ENA Timer T2 Interrupt Enable for Timer Underflow or T2A Input capture edge T2PNDB Timer T2 Interrupt Pending Flag for T2B cap- ture edge T2ENB Timer T2 Interrupt Enable for T2B Input capture edge 10.9.5 T3CNTRL Register (Address X'00B6) T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB Bit 7 Bit 0 The T3CNTRL register contains the following bits: T3C3 Timer T3 mode control bit T3C2 Timer T3 mode control bit T3C1 Timer T3 mode control bit T3C0 Timer T3 Start/Stop control in timer modes 1 and 2, Timer T3 Underflow Interrupt Pending Flag in timer mode 3 T3PNDA Timer T3 Interrupt Pending Flag (Autoreload RA in mode 1, T3 Underflow in mode 2, T3A capture edge in mode 3) T3ENA Timer T3 Interrupt Enable for Timer Underflow or T3A Input capture edge T3PNDB Timer T3 Interrupt Pending Flag for T3B cap- ture edge T3ENB Timer T3 Interrupt Enable for T3B Input capture edge www.national.com 27 |
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