COP8CDR9KMT7 datasheet(28/84 Pages) NSC

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10.0 Functional Description

(Continued)

10.9.6 HSTCR Register (Address X'00AF)

Reserved

T3HS

T2HS

Bit 7

Bit 0

The HSTCR register contains the following bits:

T3HS Places Timer T3 in High Speed Mode.

T2HS Places Timer T2 in High Speed Mode.

10.9.7 ITMR Register (Address X'00CF)

LSON

HSON

DCEN

CCKS

RSVD

ITSEL2

ITSEL1

ITSEL0

Bit 7

Bit 0

The ITMR register contains the following bits:

LSON

Turns the low speed oscillator on or off.

HSON

Turns the high speed oscillator on or off.

DCEN

Selects the high speed oscillator or the low

speed oscillator as the Idle Timer Clock.

CCKSEL Selects the high speed oscillator or the low

speed oscillator as the primary CPU clock.

RSVD

This bit is reserved and must be 0.

ITSEL2

Idle Timer period select bit.

ITSEL1

Idle Timer period select bit.

ITSEL0

Idle Timer period select bit.

10.9.8 ENAD Register (Address X'00CB)

ADCH3 ADCH2

ADCH1

ADCH0

ADMOD

MUX

PSC

ADBSY

Channel Select

Mode

Select

Mux Out

Prescale

Busy

Bit 7

Bit 0

The ENAD register contains the following bits:

ADCH3 ADC channel select bit

ADCH2 ADC channel select bit

ADCH1 ADC channel select bit

ADCH0 ADC channel select bit

ADMOD Places the ADC in single-ended or differential

mode.

MUX

Enables the ADC multiplexor output.

PSC

Switches the ADC clock between a divide by one

or a divide by sixteen of MCLK.

ADBSY Signifies that the ADC is currently busy perform-

ing a conversion. When set by the user, starts a

conversion.

11.0 In-System Programming

11.1 INTRODUCTION

This device provides the capability to program the program

memory while installed in an application board. This feature

is called In System Programming (ISP). It provides a means

of ISP by using the MICROWIRE/PLUS, or the user can

provide his own, customized ISP routine. The factory in-

stalled ISP uses the MICROWIRE/PLUS port. The user can

provide his own ISP routine that uses any of the capabilities

of the device, such as USART, parallel port, etc.

11.2 FUNCTIONAL DESCRIPTION

The organization of the ISP feature consists of the user flash

program memory, the factory boot ROM, and some registers

dedicated to performing the ISP function. See Figure 13 for

a simplified block diagram. The factory installed ISP that

uses MICROWIRE/PLUS is located in the Boot ROM. The

size of the Boot ROM is 1K bytes and also contains code to

facilitate in system emulation capability. If a user chooses to

write his own ISP routine, it must be located in the flash

program memory.

As described in 10.5 OPTION REGISTER, there is a bit,

FLEX, that controls whether the device exits RESET execut-

ing from the flash memory or the Boot ROM. The user must

program the FLEX bit as appropriate for the application. In

the erased state, the FLEX bit = 0 and the device will

power-up executing from Boot ROM. When FLEX = 0, this

assumes that either the MICROWIRE/PLUS ISP routine or

external programming is being used to program the device. If

10137417

FIGURE 13. Block Diagram of ISP

COP8CDR9KMT7 Datasheet(PDF) 28 Page - National Semiconductor (TI)

COP8CDR9KMT7 Datasheet(HTML) 28 Page - National Semiconductor (TI)

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