COP8CDR9KMT7 datasheet(17/84 Pages) NSC

17 / 84 page

8.0 Electrical Characteristics (Continued)

AC Electrical Characteristics (−40˚C

≤ T

A ≤ +125˚C) (Continued)

Note 11: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC

and outputs driven low but not connected to a load.

Note 12: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F,

G0, and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to VCC; A/D converter and

clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.

Note 13: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC

when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins

must be limited to < (VCC +7V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.

Note 14: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.

Note 15: Absolute Maximum Ratings should not be exceeded.

Note 16: Vcc must be valid and stable before G6 is raised to a high voltage.

A/D Converter Electrical Characteristics (−40˚C

≤ T

A ≤ +125˚C)

(Single-ended mode only)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter

Conditions

Min

Typ

Max

Units

Resolution

Bits

DNL

CC =5V

±1

LSB

INL

CC =5V

±3

LSB

Offset Error

CC = 5V

+2.5, −1

LSB

Gain Error

CC = 5V

+0.5, −2.5

LSB

Input Voltage Range

4.5V

≤ V

CC < 5.5V

Analog Input Leakage Current

0.5

µA

Analog Input Resistance (Note 9)

Ω

Analog Input Capacitance

7pF

Conversion Clock Period

4.5V

≤ V

CC < 5.5V

0.8

µs

Conversion Time (including S/H Time)

A/D

Conversion

Clock

Cycles

Operating Current on AV

CC = 5.5V

0.2

0.6

Note 17: Resistance between the device input and the internal sample and hold capacitance.

10137405

FIGURE 1. MICROWIRE/PLUS Timing

COP8CDR9KMT7 Datasheet(PDF) 17 Page - National Semiconductor (TI)

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