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PARALLEL INTERFACE

LDAC FUNCTION

UPDATE SEQUENCE

READBACK

RST

DAC8544

SLAS420 – MAY 2004

THEORY OF OPERATION (continued)

The DAC8544 provides a 16-bit parallel interface and supports both writing to and reading from the DAC input

register. (See the timing characteristics section for detailed information for a typical write or read operation.) In

addition to the data, CS, and R/W inputs, the DAC8544's interface also provides power down, LDAC, and

reset/reset-select control. Table 1 and Table 2 show the control signal actions and data format, respectively.

These features are discussed in more detail in the remaining sections.

Table 1. DAC8544 CONTROL SIGNAL SUMMARY

CS

R/W

LDAC

RST

PD

ACTION

H

X

X

X

X

↓

L

X

H,L

H

Write initiated, present input data to the bus.

↓

H

X

H,L

H

Read initiated, data from input register is presented to data bus.

↑

X

X

H,L

H

Input data is latched when writing to the device.

X

X

↑

H,L

H

X

X

X

↑

H

X

X

X

X

L

(1)

Only disables 16-bit data I/O interface. Other control lines remain active.

The DAC8544 is designed using a double-buffered architecture. A write operation (rising edge of CS while R/W

is low) transfers data from the data input pins into the input register. The data is held in the input register until a

rising-edge is detected on the LDAC input. This rising-edge signal transfers the data from the input register to the

DAC register. On issuance of the rising LDAC edge, the output of the DAC8544 begins settling to the newly

written data value presented to the DAC register. Data in the input register is not changed when an LDAC rising

edge occurs.

For regular operation, R/W pin should be kept low while CS is kept high. Then, the 16-bit digital data should be

applied to the input bus. The channel selection should then be asserted by setting the A0 and A1 pins. The

falling edge of CS enables the device. Once the data is stable and the channels are selected, the first rising edge

of the CS signal latches the data to the input register of the selected channel. After the data is latched to the

input register, the rising edge of the LDAC signal updates all four channels simultaneously with existing data from

their corresponding input register.

For read-back operation, the user first releases the 16-bit bus, while CS is high. Then, the DAC channel should

be selected using the A0 and A1 pins. R/W pin is then brought high to enable read-back operation. Following the

falling edge of CS, the data from the selected channel (buffer data) is output on the bus.

The RST input controls the reset of the DAC register and, consequently, the DAC output, but does not change

the input register. The reset operation is edge-triggered by a low-to-high transition on the RST pin. Once a rising

edge on RST is detected, the DAC output settles to the zero code. Application of a valid reset signal to the DAC

does not overwrite existing data in the input register.

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