ADS8342

SBAS277 – MAY 2003

www.ti.com

11

Over recommended operating free-air temperature range at –40

°C to +85°C, and BVDD = +5V, unless otherwise noted.

ADS8342I

ADS8342IB

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNIT

Conversion time

tCONV

17

:

tC1

Acquisition time

tACQ

3

:

tC1

CLK period

tC1

0.2

2

:

:

µs

CLK high time (for 5MHz clock frequency)

tW1

25

:

ns

CLK low time (for 5MHz clock frequency)

tW2

40

:

ns

CONV low to CLK high

tD1

40

:

ns

CONV low time

tW3

40

:

ns

CS low to CONV low

tD2

0

:

ns

CONV low to BUSY high

tD3

70

:

ns

CONV and CS high to 2nd CLK high(3)

tD4

80

:

ns

18 CLK high to BUSY low

tD5

60

:

ns

18 CLK low to CS low

tD6

0

:

ns

CS low to RD low

tD7

0

:

ns

CS high time

tW4

40

:

ns

RD low time

tW5

40

:

ns

RD low to data valid

tD8

25

:

ns

RD high to CS high

tD9

0

:

ns

Data hold from RD high

tD10

5

:

ns

RD high to CONV low

tD11

1.5

:

tC1

RD high time

tW6

40

:

ns

BYTE change to RD low(4)

tD12

20

:

ns

A0 and A1 to CONV low

tD13

40

:

ns

A0 and A1 hold to CONV high

tD14

10

:

ns

(1) All input signals are specified with rise and fall times of 5ns, tR = tF = 5ns (10% to 90% of BVDD), and timed from a voltage level of (VIL + VIH)/2.

(2) See timing diagram in Figure 2.

(3) CS can stay low during conversion. If it is not held low, then CS high to 2nd CS high must be > 80ns (tD4)

(4) BYTE is asynchronous. When BYTE is 0, bits 15 through 0 appear at DB15–DB0. When BYTE is 1, bits 15 through 8 appear on DB7–DB0.

RD may remain low between changes in BYTE.