DDC232 datasheet(14/34 Pages) TI1

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RESET

> 1

µs

DDC232

SBAS331D – AUGUST 2004 – REVISED APRIL 2010

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DIGITAL INTERFACE

DVALID

eliminates

any

concern

about

this

relationship. If the data read back is timed from

The digital interface of the DDC232 outputs the digital

CONV, make sure to wait for the required amount of

results via a synchronous serial interface consisting

time. For Continuous mode, this time is given by

of a data clock (DCLK), a valid data pin (DVALID), a

tCMDR. For Noncontinuous mode, use tNCDR1 or tNCDR2,

serial data output pin (DOUT), and a serial data input

as appropriate. See Table 9 for details.

pin (DIN). The integration and conversion process is

fundamentally independent of the data retrieval

Reset (RESET)

process.

Consequently,

the

CLK

and

DCLK

frequencies need not be the same, though for best

The DDC232 is reset asynchronously by taking the

performance, it is highly recommended that they be

RESET input low, as shown in Figure 9. Make sure

derived from the same clocking source to keep the

the release pulse is at least 1ms wide. After resetting

phase relationship constant. DIN is only used when

the DDC232, wait at least four conversions before

multiple converters are cascaded and should be tied

using the data. It is very important that RESET is

to DGND otherwise. Depending on tINT, CLK, and

glitch-free to avoid unintentional resets.

DCLK,

possible

daisy-chain

multiple

converters. This greatly simplifies the interconnection

and routing of the digital outputs in those applications

where a large number of converters are needed.

Configuration of the DDC232 is set by a dedicated

addressed

using

the

DIN_CFG

and

CLK_CFG pins.

Figure 9. Reset Timing

System and Data Clocks (CLK and CONV)

The system clock is supplied to CLK and the data

Conversion Rate

clock is supplied to DCLK. It is recommended that the

The conversion rate of the DDC232 is set by a

CLK pin be driven by a free-running clock source

combination of the integration time (determined by

(that is, do not start and stop CLK between

the user) and the speed of the A/D conversion

conversions). Make sure the clock signals are

process. The A/D conversion time is primarily a

clean—avoid

overshoot

ringing.

For

best

function of the system clock (CLK) speed. One A/D

performance, generate both clocks from the same

conversion cycle encompasses the conversion of two

clock source. DCLK should be disabled by taking it

signals (one side of each dual integrator feeding the

low after the data has been shifted out or while

modulator) and the reset time for each of the

CONV is transitioning.

integrators involved in the two conversions. In most

When using multiple DDC232s, pay close attention to

situations, the A/D conversion time is shorter than the

the DCLK distribution on the printed circuit board

integration time. If this condition exists, the DDC232

(PCB). In particular, make sure to minimize skew in

will operate in the continuous mode. When the

the DCLK signal because this can lead to timing

DDC232 is in the continuous mode, the sensor output

violations in the serial interface specifications. See

is continuously integrated by one of the two sides of

the Cascading Multiple Converters section for more

each input.

details.

In the event that the A/D conversion takes longer

than the integration time, the DDC232 will switch into

Data Valid (DVALID)

a Noncontinuous mode. In Noncontinuous mode, the

The DVALID signal indicates that data are ready.

A/D converter is not able to keep pace with the speed

Data retrieval may begin after DVALID goes low. This

the

integration

process.

Consequently,

the

signal is generated using an internal clock divided

integration process is periodically halted until the

down from the system clock, CLK. The phase

digitizing process catches up. These two basic modes

relationship between this internal clock and CLK is

operation

for

the

DDC232—Continuous

and

set when power is first applied and is random. Since

Noncontinuous modes—are described below.

the user must synchronize CONV with CLK, the

DVALID signal will have a random phase relationship

with CONV. This uncertainty is ±1/fCLK. Polling

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