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DLP2010

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DLPS046B – JULY 2014 – REVISED JULY 2016

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and

VRESET. DMD power-up and power-down sequencing is strictly controlled by the DLPA2000 or DLPA2005

device.

CAUTION

For reliable operation of the DMD, the following power supply sequencing

requirements must be followed. Failure to adhere to the prescribed power-up and

power-down procedures may affect device reliability.

VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated

during power-up and power-down operations. Failure to meet any of the below

requirements will result in a significant reduction in the DMD’s reliability and lifetime.

Refer to Figure 23. VSS must also be connected.

9.1 Power Supply Power-Up Procedure

•

During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET

voltages are applied to the DMD.

•

During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the

specified limit shown in Recommended Operating Conditions. Refer to Table 3 and the Layout Example for

power-up delay requirements.

•

During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled

at operating voltage.

•

During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow

the requirements listed previously and in Figure 22.

9.2 Power Supply Power-Down Procedure

•

Power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be

supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.

•

During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement

that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended

Operating Conditions (Refer to Note 2 for Figure 22).

•

During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in

Recommended Operating Conditions.

•

During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS.

•

Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements listed previously and in Figure 22.

DLPA2000 Datasheet(PDF) 29 Page - Texas Instruments

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