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DLP2010

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DLPS046B – JULY 2014 – REVISED JULY 2016

Product Folder Links: DLP2010

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(1)

Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 3.

(2)

Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 3.

(3)

Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

(4)

Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN

NOM

MAX

UNIT

LPSDR

(30% to 80%) × VDD, Figure 3

1

3

V/ns

(70% to 20%) × VDD, Figure 3

1

3

V/ns

(20% to 80%) × VDD, Figure 3

0.25

V/ns

(80% to 20%) × VDD, Figure 3

0.25

V/ns

Cycle time LS_CLK,

Figure 2

7.7

8.3

ns

Pulse duration LS_CLK

high

50% to 50% reference points,Figure 2

3.1

ns

Pulse duration LS_CLK

low

50% to 50% reference points, Figure 2

3.1

ns

Setup time

LS_WDATA valid before LS_CLK

↑, Figure 2

1.5

ns

Hold time

LS_WDATA valid after LS_CLK

↑, Figure 2

1.5

ns

Setup time + Hold time, Figure 2

3

ns

For each 0.25 V/ns reduction in slew rate below

1 V/ns, Figure 5

0.35

ns

SubLVDS

Rise slew rate

20% to 80% reference points, Figure 4

0.7

1

V/ns

Fall slew rate

80% to 20% reference points, Figure 4

0.7

1

V/ns

Cycle time LS_CLK,

Figure 6

1.61

1.67

ns

Pulse duration DCLK high

50% to 50% reference points, Figure 6

0.71

ns

Pulse duration DCLK low

50% to 50% reference points, Figure 6

0.71

ns

Setup time

D(0:3) valid before

DCLK

↑ or DCLK ↓, Figure 6

Hold time

D(0:3) valid after

DCLK

↑ or DCLK ↓, Figure 6

Window time

Setup time + Hold time, Figure 6, Figure 7

0.3

ns

ENABLE+REFGEN

2000

ns