DLPA2000 datasheet(32/41 Pages) TI1

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DLP2010

DLPS046B – JULY 2014 – REVISED JULY 2016

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10 Layout

10.1 Layout Guidelines

There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board

connector to a flex cable. Flex cable provides the interface of data and Ctrl signals between the DLPC343x

controller and the DLP2010 DMD. For detailed layout guidelines refer to the layout design files. Some layout

guideline for the flex cable interface with DMD are:

•

Match lengths for the LS_WDATA and LS_CLK signals.

•

Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 24.

•

Minimum of 100-nF decoupling capacitor close to VBIAS. Capacitor C4 in Figure 25.

•

Minimum of 100-nF decoupling capacitor close to VRST. Capacitor C6 in Figure 25.

•

Minimum of 220-nF decoupling capacitor close to VOFS. Capacitor C7 in Figure 25.

•

Optional minimum 200- to 220-nF decoupling capacitor to meet the ripple requirements of the DMD. C5 in

Figure 25.

•

Minimum of 100-nF decoupling capacitor close to Vcci. Capacitor C1 in Figure 25.

•

Minimum of 100-nF decoupling capacitor close to both groups of Vcc pins, for a total of 200 nF for Vcc.

Capacitor C2/C3 in Figure 25.

10.2 Layout Example

Figure 24. High-Speed (HS) Bus Connections

DLPA2000 Datasheet(PDF) 32 Page - Texas Instruments