3935

THREE-PHASE POWER

MOSFET CONTROLLER

www.allegromicro.com

9

Terminal Descriptions

AHI/BHI/CHI. Direct control of high-side gate outputs GHA/

GHB/GHC. Logic “1” drives the gate “on”. Logic ”0” pulls the

gate down, turning off the external power MOSFET. Internally

pulled down when terminal is open.

ALO/BLO/CLO. Direct control of low-side gate outputs GLA/

GLB/GLC. Logic “1” drives the gate “on”. Logic ”0” pulls the

gate down, turning off the external power MOSFET. Internally

pulled down when terminal is open.

BOOSTD. Boost converter switch drain connection.

BOOSTS. Boost converter switch source connection.

CA/CB/CC. High-side connection for bootstrap capacitor,

positive supply for high-side gate drive. The bootstrap capacitor

is charged to VREG when the output Sx terminal is low. When

the output swings high, the voltage on this terminal rises with

the output to provide the boosted gate voltage needed for n-

channel power MOSFETs.

CSN. Input for current-sense, differential amplifier, inverting,

negative side. Kelvin connection for ground side of current-

sense resistor.

CSOUT. Amplifier output voltage proportional to current

sensed across an external low-value resistor placed in the

ground-side of the power FET bridge.

CSP. Input for current-sense differential amplifier, non-

inverting, positive side. Connected to positive side of sense

resistor.

ENABLE. Logic “0” disables the gate control signals and

switches off all the gate drivers “low” causing a “coast”. Can be

used in conjunction with the gate inputs to PWM the load

current. Internally pulled down when terminal is open.

FAULT. Diagnostic logic output signal, when “low” indicates

that one or more fault condition have occurred.

GHA/GHB/GHC. High-side gate-drive outputs for n-channel

MOSFET drivers. External series gate resistors can control slew

rate seen at the power driver gate; thereby, controlling the di/dt

and dv/dt of Sx outputs.

GLA/GLB/GLC. Low-side gate drive outputs for external, n-

channel MOSFET drivers. External series gate resistors can

control slew rate.

GND. Ground or negative side of VDD and VBAT supplies.

LSS. Low-side gate driver returns. Connects to the common

sources in the low-side of the power MOSFET bridge.

OVFLT. Logic “1” means that the VBAT exceeded the VBAT

overvoltage trip point set by OVSET level. It will recover after

a hysteresis below that maximum value. Normally has a high-

impedance state.

OVSET. A positive, dc level that controls the VBAT overvolt-

age trip point. Usually, provided from precision resistor divider

network between V

preset value. When terminal is open, sets unspecified but high

overvoltage trip point.

SA/SB/SC. Directly connected to the motor terminals, these

terminals sense the voltages switched across the load and are

connected to the negative side of the bootstrap capacitors. Also,

are the negative supply connection for the floating, high-side

drivers.

UVFLT. Logic “1” means that VBAT is below its minimum

value and will recover after a hysteresis above that minimum

value. Has a high-impedance state. [If UVFLT and OVFLT are

both in high-impedance state; then, at least, a thermal shutdown

or VDD undervoltage has occurred.]

VBAT. Battery voltage, positive input and is usually connected

to the motor voltage supply.

VBOOST. Boost converter output, nominally 16 V, is also

input to regulator for VREG. Has internal boost current and

boost voltage control loops. In high-voltage systems is approxi-

mately one diode drop below V

VDD. Logic supply, nominally +5 V.

VDRAIN. Kelvin connection for drain-to-source voltage

monitor and is connected to high-side drains of MOSFET

bridge. High impedance when terminal is open and registers as

a short-to-ground fault on all motor phases.

VDSTH. A positive, dc level that sets the drain-to-source

monitor threshold voltage. Internally pulled down when

terminal is open.

VREG. High-side, gate-driver supply, nominally, 13.5 V. Has

low-voltage dropout (LDO) feature.