REV. 0

–22–

AD1980

SPDIF Control Register (Index 3Ah)

Reg

No. Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

3Ah SPDIF

V

X

SPSR1

SPSR0

L

CC6

CC5 CC4

CC3

CC2

CC1

CC0

PRE

COPY

/AUD PRO

2000h

Control

All registers not shown and bits containing an X are assumed to be reserved.

Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the

exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF Bit in Register 2Ah is “0”). This ensures that control and status

information starts up correctly at the beginning of SPDIF transmission.

PRO

Professional. “1” indicates professional use of channel status, “0” indicates consumer.

/AUD

Non-Audio. “1” indicates data is non PCM format, “0” indicates data is PCM.

COPY

Copyright. “1” indicates copyright is asserted, “1” indicates copyright is not asserted.

PRE

Pre-emphasis. “1” indicates filter pre-emphasis is 50

µs/15 µs, “0” indicates pre-emphasis is none.

CC[6-0]

Category Code. Programmed according to IEC standards, or as appropriate.

LGeneration Level. Programmed according to IEC standards, or as appropriate.

SPSR[1,0]

SPDIF Transmit Sample Rate:

SPSR[1:0] = “00” Transmit Sample Rate = 44.1 kHz

SPSR[1:0] = “01” Reserved

SPSR[1:0] = “10” Transmit Sample Rate = 48 kHz (default)

SPSR[1:0] = “11” Not supported.

VValidity. This bit affects the Validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF

transmitter to maintain connection during error or mute conditions.

V = 1 Each SPDIF subframe (L+R) has Bit 28 set to “1.” This tags both samples as invalid.

V = 0 Each SPDIF subframe (L+R) has Bit 28 set to “0” for valid data and “1” for invalid data (error condition).

Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext’d Audio Stat/Ctrl) will force the Va-

lidity flag low, marking both samples as valid.

Table VIII. Settings for Surround Register

Control Bits

Surround Volume (38h)

Left Surround D[13:8]

Right Surround D[5:0]

D15/D7

WRITE

READBACK

Function with AC97NC = 0

Function with AC97NC = 1

0

00 0000

00 0000

0 dB Gain

12 dB Gain

0

00 1111

00 1111

–22 dB Gain

–10.5 dB Gain

0

01 1111

01 1111

–46.5 dB Gain

–34.5 dB Gain

0

1x xxxx

01 1111

–46.5 dB Gain

Not Applicable

1

xx xxxx

xx xxxx

Muted

Muted