ADF4153 datasheet(19/24 Pages) AD

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ADF4153

Rev. A | Page 19 of 24

Example: In a GSM 1800 system, where 1.8 GHz RF frequency

output (RFOUT) is required, a 13 MHz reference frequency input

(REFIN) is available and a 200 kHz channel resolution (fRES) is

required on the RF output.

200

kHz

MHz

MOD

REF

MOD

RES

From Equation 4:

( )

[

] MHz

MHz

FPFD

(5)

(

)

;

138

≥

FRAC

INT

FRAC

INT

MHz

(6)

MODULUS

The choice of modulus (MOD) depends on the reference signal

(REFIN) available and the channel resolution (fRES) required at

the RF output. For example, a GSM system with 13 MHz REFIN

would set the modulus to 65. This means that the RF output

resolution (fRES) is the 200 kHz (13 MHz/65) necessary for GSM.

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the

noise performance of the system. Doubling the PFD frequency

usually results in an improvement in noise performance of 3 dB.

It is important to note that the PFD cannot be operated above

32 MHz due to a limitation in the speed of the Σ-Δ circuit of

the N divider.

12-BIT PROGRAMMABLE MODULUS

Unlike most other fractional-N PLLs, the ADF4153 allows the

user to program the modulus over a 12-bit range. This means

that the user can set up the part in many different

configurations for the application, when combined with the

reference doubler and the 4-bit R counter.

For example, here is an application that requires 1.75 GHz RF

and 200 kHz channel step resolution. The system has a 13 MHz

reference signal.

One possible setup is feeding the 13 MHz directly to the PFD

and programming the modulus to divide by 65. This would

result in the required 200 kHz resolution.

Another possible setup is using the reference doubler to create

26 MHz from the 13 MHz input signal. This 26 MHz is then fed

into the PFD. The modulus is now programmed to divide by

130. This also results in 200 kHz resolution and offers superior

phase noise performance over the previous setup.

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC and

GSM 1800 standards, the programmable modulus is a huge

benefit. PDC requires 25 kHz channel step resolution, whereas

GSM 1800 requires 200 kHz channel step resolution. A 13 MHz

reference signal could be fed directly to the PFD. The modulus

would be programmed to 520 when in PDC mode (13 MHz/

520 = 25 kHz). The modulus would be reprogrammed to 65 for

GSM 1800 operation (13 MHz/65 = 200 kHz). It is important

that the PFD frequency remains constant (13 MHz). This allows

the user to design one loop filter that can be used in both setups

without running into stability issues. It is the ratio of the RF

frequency to the PFD frequency that affects the loop design.

Keeping this relationship constant, instead of changing the

modulus factor, results in a stable filter.

SPURIOUS OPTIMIZATION AND FASTLOCK

As mentioned earlier, the part can be optimized for spurious

performance. However, in fast locking applications, the loop

bandwidth needs to be wide, and therefore the filter does not

provide much attenuation of the spurs. The programmable

charge pump can be used to get around this issue. The filter is

designed for a narrow-loop bandwidth so that steady-state

spurious specifications are met. This is designed using the

lowest charge pump current setting. To implement fastlock

during a frequency jump, the charge pump current is set to the

maximum setting for the duration of the jump. This has the

effect of widening the loop bandwidth, which improves lock

time. When the PLL has locked to the new frequency, the charge

pump is again programmed to the lowest charge pump current

setting. This narrows the loop bandwidth to its original cutoff

frequency to allow better attenuation of the spurs than the

wide-loop bandwidth.

PHASE RESYNC AND SPUR CONSISTENCY

Setting the RESYNC bits [S4 ,S3, S2, and S1] enables the phase

RESYNC feature. With a fractional denominator of MOD, a

fractional-N PLL can settle with any one of (2 × π)/MOD valid

phase offsets with respect to the reference input. This is

different from integer-N where the RF output always settles to

the same static phase offset with respect to the input reference,

which is zero ideally. This is not an issue in applications that

require only a consistent frequency lock. When RESYNC is

enabled, it also ensures that spur levels remain consistent when

the PLL returns to a certain frequency. This is due to the fact

that the RESYNC function resets the Σ-Δ modulator. RESYNC

is enabled by setting the S4 to S1 bits in R2 to a nonzero value.

When the S4 to S1 bits are 0, 0, 0, and 0, RESYNC is disabled.

For applications where a consistent phase relationship between

the output and reference is required (i.e., digital beam forming),

the ADF4153 can be used with the phase resync feature enabled.

This ensures that if the user programs the PLL to jump from

Frequency (and Phase) A to Frequency (and Phase) B and back

again to Frequency A, the PLL returns to the original phase

(Phase A).

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