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TMS320DM355 Datasheet(PDF) 125 Page - Texas Instruments |
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TMS320DM355 Datasheet(HTML) 125 Page - Texas Instruments |
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125 / 163 page  PCLK 2 1 3 4 4 TMS320DM355 www.ti.com SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010 5.9.1.4 VPFE Electrical Data/Timing Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode(1) (see Figure 5-23) NO. PARAMETER MIN MAX UNIT H3A not used 13.33 or P(2) 100 ns 1 tc(PCLK) Cycle time, PCLK H3A used 2P + 1 100 ns 2 tw(PCLKH) Pulse duration, PCLK high 5.7 ns 3 tw(PCLKL) Pulse duration, PCLK low 5.7 ns 4 tt(PCLK) Transition time, PCLK 3 ns (1) P = 1/SYSCLK4 in nanoseconds (ns). For example, if the SYSCLK4 frequency is 135 MHz, use P = 7.41 ns. See Section 3.5 , Device Clocking, for more information on the supported clock configurations of the DM355. (2) Use whichever value is greater. Figure 5-23. VPFE PCLK Timing Table 5-18. Timing Requirements for VPFE (CCD) Slave Mode (see Figure 5-24) DM355 NO. PARAMETER UNIT MIN MAX 5 tsu(CCDV-PCLK) Setup time, CCD valid before PCLK edge 3 ns 6 th(PCLK-CCDV) Hold time, CCD valid after PCLK edge 2 ns 7 tsu(HDV-PCLK) Setup time, HD valid before PCLK edge 3 ns 8 th(PCLK-HDV) Hold time, HD valid after PCLK edge 2 ns 9 tsu(VDV-PCLK) Setup time, VD valid before PCLK edge 3 ns 10 th(PCLK-VDV) Hold time, VD valid after PCLK edge 2 ns 11 tsu(CAM_WEN_FIELDV-PCLK) Setup time, CAM_WEN_FIELD valid before PCLK edge 3 ns 12 th(CAM_WEN_FIELDV-PCLK) Hold time, C_WEN_FIELD valid after PCLK edge 2 ns Copyright © 2007–2010, Texas Instruments Incorporated DM355 Peripheral Information and Electrical Specifications 125 Submit Documentation Feedback Product Folder Link(s): TMS320DM355 |
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