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TMS320DM355 Datasheet(PDF) 129 Page - Texas Instruments |
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TMS320DM355 Datasheet(HTML) 129 Page - Texas Instruments |
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129 / 163 page  1 PCLK 2 3 7 5 6 4 8 EXTCLK 4 8 TMS320DM355 www.ti.com SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010 • Master/Slave Operation • Internal Color Bar Generation (100%/75%) • YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input 5.9.2.3 VPBE Electrical Data/Timing Table 5-21. Timing Requirements for VPBE CLK Inputs (see Figure 5-27) DM355 NO. PARAMETER UNIT MIN MAX 1 tc(PCLK) Cycle time, PCLK(1) 13.33 160 ns 2 tw(PCLKH) Pulse duration, PCLK high 5.7 ns 3 tw(PCLKL) Pulse duration, PCLK low 5.7 ns 4 tt(PCLK) Transition time, PCLK 3 ns 5 tc(EXTCLK) Cycle time, EXTCLK 13.33 160 ns 6 tw(EXTCLKH) Pulse duration, EXTCLK high 5.7 ns 7 tw(EXTCLKL) Pulse duration, EXTCLK low 5.7 ns 8 tt(EXTCLK) Transition time, EXTCLK 3 ns (1) For timing specifications relating to PCLK see Table 5-17 , Timing Requirements for VPFE PCLK Master/Slave Mode. Figure 5-27. VPBE PCLK and EXTCLK Timing Table 5-22. Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK(1) (2) (3) (see Figure 5-28) DM355 NO. PARAMETER UNIT MIN MAX 9 tsu(VCTLV-VCLKIN) Setup time, VCTL valid before VCLKIN edge 2 ns 10 th(VCLKIN-VCTLV) Hold time, VCTL valid after VCLKIN edge 1 ns (1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced. (2) VCTL = HSYNC, VSYNC, and FIELD (3) VCLKIN = PCLK or EXTCLK Copyright © 2007–2010, Texas Instruments Incorporated DM355 Peripheral Information and Electrical Specifications 129 Submit Documentation Feedback Product Folder Link(s): TMS320DM355 |
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