TMDS00510WS datasheet(34/61 Pages) TI1

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BE1

BE2

BE3

BE4

SSCLK

CEx

BE[3:0]

EA[21:2]

ED[31:0]

SSADS

SSOE

SSWE

SMJ320C6701-SP

SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013

www.ti.com

SYNCHRONOUS-BURST MEMORY TIMING

Timing Requirements for Synchronous-Burst SRAM Cycles (Full-Rate SSCLK)

(see Figure 14)

NO.

MIN

MAX

UNIT

tsu(EDV–SSCLKH)

Setup time, read EDx valid before SSCLK high

2.6

th(SSCLKH–EDV)

Hold time, read EDx valid after SSCLK high

1.5

Switching Characteristics for Synchronous-burst SRAM Cycles

(1) (Full-Rate SSCLK)

(see Figure 14 and Figure 15)

NO.

PARAMETER

MIN

MAX

UNIT

tosu(CEV–SSCLKH)

Output setup time, CEx valid before SSCLK high

0.5P – 1.5

toh(SSCLKH–CEV)

Output hold time, CEx valid after SSCLK high

0.5P – 2.5

tosu(BEV–SSCLKH)

Output setup time, BEx valid before SSCLK high

0.5P – 1.6

toh(SSCLKH–BEIV)

Output hold time, BEx invalid after SSCLK high

0.5P – 2.5

tosu(EAV–SSCLKH)

Output setup time, EAx valid before SSCLK high

0.5P – 1.7

toh(SSCLKH–EAIV)

Output hold time, EAx invalid after SSCLK high

0.5P – 2.5

tosu(ADSV–SSCLKH)

Output setup time, SSADS valid before SSCLK high

0.5P – 1.5

toh(SSCLKH–ADSV)

Output hold time, SSADS valid after SSCLK high

0.5P – 2.5

tosu(OEV–SSCLKH)

Output setup time, SSOE valid before SSCLK high

0.5P – 1.5

toh(SSCLKH–OEV)

Output hold time, SSOE valid after SSCLK high

0.5P – 2.5

tosu(EDV–SSCLKH)

Output setup time, EDx valid before SSCLK high

0.5P – 1.5

toh(SSCLKH–EDIV)

Output hold time, EDx invalid after SSCLK high

0.5P – 2.5

tosu(WEV–SSCLKH)

Output setup time, SSWE valid before SSCLK high

0.5P – 1.5

toh(SSCLKH–WEV)

Output hold time, SSWE valid after SSCLK high

0.5P – 2.5

(1)

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is

used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns. For CLKMODE x1,

0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for

all output hold times.

Figure 14. SBSRAM Read Timing (Full-Rate SSCLK)

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TMDS00510WS Datasheet(PDF) 34 Page - Texas Instruments

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