TMDS00510WS datasheet(49/61 Pages) TI1

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SMJ320C6701-SP

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SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013

Switching Characteristics for McBSP

(1) (2) (3)

(see Figure 31)

NO.

PARAMETER

MIN

MAX

UNIT

Delay time, CLKS high to CLKR/X high for internal

td(CKSH–CKRXH)

CLKR/X generated from CLKS input

CLKR/X

tc(CKRX)

Cycle time, CLKR/X

int

CLKR/X

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

C – 1(4)

C + 1(4)

int

td(CKRH–FRV)

Delay time, CLKR high to internal FSR valid

CLKR int

–4

CLKX int

–4

td(CKXH–FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

3(5)

16(5)

CLKX int

–3(5)

2(5)

Disable time, DX high impedance following last data bit

tdis(CKXH–DXHZ)

from CLKX high

CLKX ext

2(5)

9(5)

CLKX int

–2

td(CKXH–DXV)

Delay time, CLKX high to DX valid.

CLKX ext

Delay time, FSX high to DX valid.

FSX int

–2(5)

4(5)

td(FXH–DXV)

ONLY applies when in data delay 0 (XDATDLY = 00b)

FSX ext

2(5)

10(5)

mode.

(1)

CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing

references of that signal are also inverted.

(2)

Minimum delay times also represent minimum output hold times.

(3)

P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.

(4)

C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

(5)

This parameter is not tested.

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