TMDS00510WS datasheet(52/61 Pages) TI1

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Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

CLKX

FSX

SMJ320C6701-SP

SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013

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Timing Requirements SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

(1) (1)

(continued)

(see Figure 34)

MASTER

SLAVE

NO.

UNIT

MIN

MAX

MIN

MAX

tsu(DRV–CKXH)

Setup time, DR valid before CLKX high

2 – 3P

th(CKXH–DRV)

Hold time, DR valid after CLKX high

5 + 6P

Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

(1) (2)

(see Figure 34)

MASTER(3)

SLAVE

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

th(CKXL–FXL)

Hold time, FSX low after CLKX low(4)

L – 4

L + 4

td(FXL–CKXH)

Delay time, FSX low to CLKX high(5)

T – 4

T + 4

td(CKXL–DXV)

Delay time, CLKX low to DX valid

–4

3P + 1

5P + 17

Disable time, DX high impedance following last

tdis(CKXL–DXHZ)

–2(6)

4(6)

3P + 4(6)

5P + 17(6)

data bit from CLKX low

td(FXL–DXV)

Delay time, FSX low to DX valid

H – 2(6)

H + 3(6)

2P + 1

4P + 13

(1)

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock

frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.

(2)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3)

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

(4)

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on

FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

(5)

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master

clock (CLKX).

(6)

This parameter is not tested.

Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

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