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WM8595 Datasheet(PDF) 43 Page - Wolfson Microelectronics plc |
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WM8595 Datasheet(HTML) 43 Page - Wolfson Microelectronics plc |
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43 / 82 page  Production Data WM8595 w PD, Rev 4.2, January 2011 43 DAC1 AND DAC2 AUDIO INTERFACE CLOCK CONFIGURATION Both DACs on the WM8595 have independent audio interfaces which can be configured to select the required signals from any of the digital audio ports. The audio interfaces are not restricted to take each signal from the same digital audio ports, although the BCLK and LRCLK signals are selected together. DAC1MCLK and DAC2MCLK are always inputs to the DAC1 and DAC2 audio interfaces and are selected using DAC1MCLK_SEL[2:0] and DAC2MCLK_SEL[2:0] respectively. DAC1BCLK and DAC1LRCLK are always selected together and can are inputs to the DAC1 audio interface. DAC2BCLK and DAC2LRCLK are always selected together and are inputs to the DAC2 audio interface. DAC1BCLK and DAC1LRCLK are selected using DAC1WORDCLK_SEL[2:0], while DAC2BCLK and DAC2LRCLK are selected using DAC2WORDCLK_SEL[2:0]. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R42 AIF_MUX3 2Ah 3:1 DAC1 MCLK_ SEL[2:0] 000 DAC1 MCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 to 111 = Reserved R43 AIF_MUX4 2Bh DAC2 MCLK_ SEL[2:0] 001 DAC2 MCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 to 111 = Reserved R42 AIF_MUX3 2Ah 6:4 DAC1 WORD CLK_ SEL[2:0] 000 DAC1 BCLK and DAC LRCLK Select 000 = Use BCLK1 and LRCLK1 001 = Use BCLK2 and LRCLK2 010 to 110 = Reserved 111 = Use ADCBCLK and ADCBCLK (when ADC is master mode) R43 AIF_MUX4 2Bh DAC2 WORD CLK_ SEL[2:0] 001 DAC2 BCLK and DAC LRCLK Select 000 = Use BCLK1 and LRCLK1 001 = Use BCLK2 and LRCLK2 010 to 110 = Reserved 111 = Use ADCBCLK and ADCBCLK (when ADC is master mode) R42 AIF_MUX3 2Ah 9:7 DAC1 DIN_ SEL[2:0] 000 DAC1 DIN Select 000 = Use DACDAT1 001 = Use DACDAT2 010 to 100 = Reserved 101 = Use GPIO1 110 = Use GPIO2 111 = Reserved R43 AIF_MUX4 2Bh 9:7 DAC2 DIN_ SEL[2:0] 001 DAC2 DIN Select 000 = Use DACDAT1 001 = Use DACDAT2 010 to 100 = Reserved 101 = Use GPIO1 110 = Use GPIO2 111 = Reserved Table 35 DAC1 and DAC2 Audio Interface Clock Configuration |
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