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WM8595 Datasheet(PDF) 68 Page - Wolfson Microelectronics plc |
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WM8595 Datasheet(HTML) 68 Page - Wolfson Microelectronics plc |
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68 / 82 page ![]() WM8595 Production Data w PD, Rev 4.2, January 2011 68 R37 (25h) – Audio Interface MUX Configuration Register 1 (AIF_MUX1) Bit # 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 PORT1_UPD 0 0 Write N/A N/A N/A N/A N/A N/A N/A Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Read 0 WORDCLK1_SEL[2:0] MCLK1_SEL[2:0] 0 Write N/A N/A Default 0 0 0 0 0 0 0 0 N/A = Not Applicable (no function implemented) Function Description MCLK1_SEL[2:0] MCLK1 Pin Function Select 000 = Input to WM8595 001 = Output MCLK2 010 to 111 = Reserved WORDCLK1_SEL[2:0] BCLK1 and LRCLK1 Pins Function Select 000 = Inputs to WM8595 001 = Output BCLK2 and LRCLK2 010 to 110 = Reserved 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) PORT1_UPD Port 1 Update 0 = Latch corresponding Port 1 settings into Register Map but do not update 1 = Latch corresponding Port 1 settings into Register Map and update all simultaneously Figure 49 R37 – Audio Interface MUX Configuration Register 1 |
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