WM8595 datasheet(48/82 Pages) WOLFSON

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WM8595

Production Data

PD, Rev 4.2, January 2011

Table 39 describes the various bias control bits for power up/down control:

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R35

BIAS

23h

POBCTRL

Bias Source for Output Amplifiers

0 = Output amplifiers use master bias

1 = Output amplifiers use fast bias

VMIDTOG

VMID Power Down Characteristic

0 = Slow ramp

1 = Fast ramp

FAST_EN

Fast Bias Enable

0 = Fast bias disabled

1 = Fast bias enabled

BUFIO_

VMID Buffer Enable

0 = VMID Buffer disabled

1 = VMID Buffer enabled

SOFT_ST

VMID Soft Ramp Enable

0 = Soft ramp disabled

1 = Soft ramp enabled

BIAS_EN

Master Bias Enable

0 = Master bias disabled

1 = Master bias enabled

Also powers down VMID1C

7:6

VMID_

SEL[1:0]

VMID Resistor String Value Selection

(VMID2C only)

00 = off (no VMID)

01 = 38k

10 = 127k

11 = 12.5k

The selection is the total resistance of the

string from VREF2VDD to VREF2GND. The

VMID1C resistance is fixed at 200kΩ.

Table 39 Bias Control

GLOBAL ENABLE CONTROL

The WM8595 includes a number of enable and disable mechanisms to allow the device to be

powered on and off in a pop-free manner. A global enable control bit enables the ADC, DAC and

analogue paths.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12

ENABLE

0Ch

GLOBAL_

Device Global Enable

0 = ADC, DAC and PGA ramp control

circuitry disabled

1 = ADC, DAC and PGA ramp control

circuitry enabled

Table 40 Global Enable Control

WM8595 Datasheet(PDF) 48 Page - Wolfson Microelectronics plc

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