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WM8595 Datasheet(PDF) 13 Page - Wolfson Microelectronics plc |
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WM8595 Datasheet(HTML) 13 Page - Wolfson Microelectronics plc |
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13 / 82 page ![]() Production Data WM8595 w PD, Rev 4.2, January 2011 13 DIGITAL AUDIO INTERFACE TIMING – MASTER MODE Figure 4 Master Mode Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25˚C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information LRCLK propagation delay from BCLK falling edge tDL 4 16 ns ADCDAT (output) propagation delay from BCLK falling edge tDDA 4 16 ns DACDAT (input) setup time to BCLK rising edge tDST 22 ns DACDAT (input) hold time to BCLK rising edge tDHT 25 ns Table 4 Master Mode Audio Interface Timing |
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