WM8595 datasheet(69/82 Pages) WOLFSON

69 / 82 page

Production Data

WM8595

PD, Rev 4.2, January 2011

R38 (26h) – Audio Interface MUX Configuration Register 2 (AIF_MUX2)

Bit #

Read

PORT2_UPD

Write

N/A

Default

Bit #

Read

WORDCLK2_SEL[2:0]

MCLK2_SEL[2:0]

Write

N/A

Default

N/A = Not Applicable (no function implemented)

Function

Description

MCLK2_SEL[2:0]

MCLK2 Pin Function Select

000 = Output MCLK1

001 = Input to WM8595

010 = Output MCLK3

011 = Output MCLK4

100 = Output MCLK5

101 to 111 = Reserved

WORDCLK2_SEL[2:0]

BCLK2 and LRCLK2 Pins Function Select

000 = Output BCLK1 and LRCLK1

001 = Inputs to WM8595

010 = Output BCLK3 and LRCLK3

011 = Output BCLK4 and LRCLK4

100 = Output BCLK5 and LRCLK5

101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode)

110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode)

111 = Output ADCBCLK and ADCBCLK (when ADC is master mode)

PORT2_UPD

Port 2 Update

0 = Latch corresponding Port 2 settings into Register Map but do not update

1 = Latch corresponding Port 2 settings into Register Map and update all simultaneously

Figure 50 R38 – Audio Interface MUX Configuration Register 2

WM8595 Datasheet(PDF) 69 Page - Wolfson Microelectronics plc

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