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WM8962B Datasheet(PDF) 107 Page - Wolfson Microelectronics plc

Part # WM8962B
Description  Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers
PDF  295 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8962B Datasheet(HTML) 107 Page - Wolfson Microelectronics plc

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WM8962
Rev 4.3
107
DAC CLOCKING CONTROL
Clocking for the DACs is derived from SYSCLK. The required clock is enabled when the
SYSCLK_ENA register is set.
The DAC clock rate is configured automatically, according to the SAMPLE_RATE and MCLK_RATE
registers. See “Clocking and Sample Rates” for further details of the system clocks and associated
control registers.
Note that the DAC and the DAC signal path enhancements functions are only supported under
specific clocking configurations. The valid clocking ratios for DAC operation are identified in Table 96.
See also Table 97 for details of the supported functions for different MCLK / fs ratios.
DAC DIGITAL VOLUME CONTROL
The output level (digital volume) of each DAC can be controlled digitally over a range from -71.625dB
to +23.625dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by:
0.375
 (X-192) dB for 1  X  255;
MUTE for X = 0
The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the
DACL_VOL or DACR_VOL control data will be loaded into the respective control register, but will not
actually change the digital gain setting. Both left and right gain settings are updated when a 1 is
written to DAC_VU. This makes it possible to update the gain of both channels simultaneously.
See "DAC Digital Volume Control" section for a description of the volume update function, the zero
cross function and the timeout operation.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R10 (0Ah)
Left DAC
volume
8
DAC_VU
N/A
DAC Volume Update
Writing a 1 to this bit will cause left
and right DAC volume to be updated
simultaneously
7:0
DACL_VOL
[7:0]
C0h
(0dB)
Left DAC Digital Volume Control
00h = Digital Mute
01h = -71.625dB
02h = -71.250dB
... 0.375dB steps up to
C0h = 0dB (default)
….
FFh = 23.625dB
(See Table 62 for volume range)
R11 (0Bh)
Right DAC
volume
8
DAC_VU
N/A
DAC Volume Update
Writing a 1 to this bit will cause left
and right DAC volume to be updated
simultaneously
7:0
DACR_VOL
[7:0]
C0h
(0dB)
Right DAC Digital Volume Control
00h = Digital Mute
01h = -71.625dB
02h = -71.250dB
... 0.375dB steps up to
C0h = 0dB (default)
….
FFh = 23.625dB
(See Table 62 for volume range)
Table 61 Digital Volume Control



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