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WM8962B Datasheet(PDF) 124 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 124 Page - Wolfson Microelectronics plc |
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124 / 295 page ![]() WM8962 124 Rev 4.3 HEADPHONE OUTPUT PATHS The following sections describe all the headphone output paths and controls. For information on the speaker output paths and controls, refer to the earlier “Speaker Output Paths” section. HEADPHONE SIGNAL PATHS ENABLE The WM8962 headphone drivers incorporate SilentSwitch technology which enables pops normally associated with Start-Up, Shut-Down or signal path control to be suppressed. To achieve maximum benefit from these features, careful attention is required to the sequence and timing of these controls. Note that, under the recommended usage conditions of the WM8962, these features will be configured by running the default Start-Up and Shut- Down sequences as described in the “Control Write Sequencer ” section. In these cases, the user does not need to set these register fields directly. The Headphone output drivers can be actively switched to AGND through internal resistors if desired. This is desirable at start-up in order to achieve a known condition prior to enabling the output. This is also desirable in shutdown to prevent the external connections from being affected by the internal circuits. The HPOUTL and HPOUTR outputs are shorted to AGND by default; the short circuit is removed on each of these paths by setting the applicable fields HP1L_RMV_SHORT and HP1R_RMV_SHORT. The ground-referenced Headphone output drivers are designed to suppress pops and clicks when enabled or disabled. However, it is necessary to control the drivers in accordance with a defined sequence in start-up and shut-down to achieve the pop suppression. It is also necessary to schedule the DC Servo offset correction at the appropriate point in the sequence (see “DC Servo”). Table 75 and Table 76 describe the recommended sequences for enabling and disabling these output drivers. SEQUENCE HPOUT ENABLE Step 1 HP1L_ENA = 1 HP1R_ENA = 1 Step 2 20 μs delay Step 3 HP1L_ENA_DLY = 1 HP1R_ENA_DLY = 1 Step 4 DC offset correction Step 5 HP1L_ENA_OUTP = 1 HP1R_ENA_OUTP = 1 Step 6 20 μs delay Step 7 HP1L_RMV_SHORT = 1 HP1R_RMV_SHORT = 1 Table 75 Headphone Output Enable Sequence SEQUENCE HPOUT DISABLE Step 1 HP1L_RMV_SHORT = 0 HP1R_RMV_SHORT = 0 Step 2 20 μs delay Step 3 HP1L_ENA = 0 HP1L_ENA_DLY = 0 HP1L_ENA_OUTP = 0 HP1R_ENA = 0 HP1R_ENA_DLY = 0 HP1R_ENA_OUTP = 0 Table 76 Headphone Output Disable Sequence The register bits relating to pop suppression control are defined in Table 77. |
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