WM8962B datasheet(125/295 Pages) WOLFSON

125 / 295 page

WM8962

Rev 4.3

125

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R69 (45h)

Analogue

HP 0

HP1L_RMV_SHO

Removes HP1L short

0 = HP1L short enabled

1 = HP1L short removed

For pop-free operation, this bit should

be set to 1 as the final step in the

HP1L Enable sequence.

HP1L_ENA_OUT

Enables HP1L output stage

0 = Disabled

1 = Enabled

For pop-free operation, this bit should

be set to 1 after the DC offset

cancellation has been performed.

HP1L_ENA_DLY

Enables HP1L intermediate stage

0 = Disabled

1 = Enabled

For pop-free operation, this bit should

be set to 1 after the output signal path

has been configured, and before the

DC Offset cancellation is scheduled

This bit should be set with at least

20us delay after HP1L_ENA.

HP1L_ENA

Enables HP1L input stage

0 = Disabled

1 = Enabled

For pop-free operation, this bit should

be set as the first stage of the HP1L

Enable sequence.

HP1R_RMV_SHO

Removes HP1R short

0 = HP1R short enabled

1 = HP1R short removed

For pop-free operation, this bit should

be set to 1 as the final step in the

HP1R Enable sequence.

HP1R_ENA_OUT

Enables HP1R output stage

0 = Disabled

1 = Enabled

For pop-free operation, this bit should

be set to 1 after the DC offset

cancellation has been performed.

HP1R_ENA_DLY

Enables HP1R intermediate stage

0 = Disabled

1 = Enabled

For pop-free operation, this bit should

be set to 1 after the output signal path

has been configured, and before the

DC Offset cancellation is scheduled

This bit should be set with at least

20us delay after HP1R_ENA.

HP1R_ENA

Enables HP1R input stage

0 = Disabled

1 = Enabled

For pop-free operation, this bit should

be set as the first stage of the HP1R

Enable sequence.

Table 77 Headphone Output Signal Paths Control

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