WM8962B datasheet(171/295 Pages) WOLFSON

171 / 295 page

WM8962

Rev 4.3

171

For each PLL, the integer value, N, is held in the PLLn_N register fields, and is used in both Integer

and Fractional Modes. The fractional portion, K, is only valid in Fractional Mode when enabled by the

field PLLn_FRAC. The value of K is held in the PLLn_K register fields.

It is recommended that PLL Fractional mode is enabled at all times (PLLn_FRAC = 1). Power

consumption in the PLL is reduced in integer mode (PLLn_FRAC = 0). However, the performance

may also be reduced, with increased noise or jitter on the output.

The FLL output frequency is generated according to the following equation:

FOUT = FVCO / (2 x PLLn_OUTDIV)

The PLL operating frequency, FVCO , is set according to the following equation:

FVCO = (FREF x N.K / 2)

FREF is the input frequency (typically 24MHz on the WM8962).

FVCO must be in the range 90-100 MHz. Note that frequencies that do not lie within this range cannot

be guaranteed across the full range of device operating temperatures.

The value of the PLLn_OUTDIV registers must be set depending on the required output frequency,

ensuring that the respective FVCO frequency is within the recommended operating limits. The

supported configurations are noted in Table 116.

Note that the CLKOUTn output frequencies can also be controlled by the CLKOUTn_DIV registers, as

defined in Table 109; these dividers extend the range of clock frequencies that can be output on the

CLKOUT pins.

Note that, when PLL3 is selected as the SYSCLK source, the frequency can also be controlled by the

PLL_SYSCLK_DIV register, as described in Table 98; this divider provides flexibility in generating the

necessary internal and external clock frequencies.

OUTPUT FREQUENCY FOUT

PLLn_OUTDIV (PLL2, 3, 4)

45 MHz - 50 MHz

PLLn_OUTDIV = 1 (divide by 2)

22.5 MHz - 25 MHz

PLLn_OUTDIV = 2 (divide by 4)

Table 116 Selection of PLLn_OUTDIV

In order to determine the remaining PLL parameters, the PLL operating frequency, FVCO, must be

calculated, as given by the following equation:

FVCO = (FOUT x 2 x PLLn_OUTDIV)

The PLL frequency ratio N.K can then be determined as follows:

N.K = FVCO x 2 / FREF

The PLL frequency ratio N.K is the real number represented by the register fields PLLn_N and

PLLn_K (where n is 2 or 3, depending on the applicable PLL). The field PLLn_N is an integer (LSB =

1); PLLn_K is the fractional portion of the number (MSB = 0.5). The fractional portion is only valid in

Fractional Mode, when enabled by the field PLLn_FRAC.

If N.K is an integer (PLL_K = 0), then PLL integer mode should be selected, ie. PLLn_FRAC = 0.

Power consumption in the PLL is reduced in integer mode.

In N.K is not an integer (PLL_K > 0), the PLL fractional mode must be selected, ie. PLLn_FRAC = 1.

For PLL stability, input frequencies and divisions must be chosen so that 5

 N  13. Best

performance is achieved for 7

 N 9. Also, the PLL performs best when F

VCO is set between 90MHz

and 100MHz.

WM8962B Datasheet(PDF) 171 Page - Wolfson Microelectronics plc

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