WM8962B datasheet(175/295 Pages) WOLFSON

175 / 295 page

WM8962

Rev 4.3

175

GENERAL PURPOSE INPUT/OUTPUT (GPIO)

The WM8962 provides four multi-function pins which can be configured to provide a number of

different functions. There are two digital output pins on the DBVDD power domain. PLLVDD must also

be present for correct functionality. The GPIO pins are:



CLKOUT2/GPIO2



CLKOUT3/GPIO3

There are two digital input/output pins on the DBVDD power domain. DCVDD must also be present for

correct functionality. The GPIO pins are:



GPIO5



¯¯ / GPIO6

Note that, under default conditions, the GPIO5 pin is used as an input to the clocking control

functions. The affected registers are described in the “Clocking and Sample Rates” and “Internal /

External Clock Generation

” sections. It is important that this input is held in a defined logic state (logic

‘0’ or logic ‘1’) during start-up; it must not be left floating. Normal GPIO5 functionality can be enabled

after start-up, as described below.

If GPIO functionality is required on the GPIO5 pin, then the CLKREG_OVD bit must be set to ‘1’ in

order to select normal read/write control of all the clocking registers, and to permit GPIO functions.

If the CLKREG_OVD bit is set to ‘0’ (default), then the GPIO5 control register (R516) must not be

changed from the default value.

The GPIO5 pin must be held in a defined logic state (logic ‘0’ or logic

‘1’) whenever the pin is configured as an input, including whenever CLKREG_OVD = 0.

Under default conditions, the GPIO2 pin is configured as the CLKOUT2 function, supporting the PLL2

output. For GPIO2 functionality, set CLKREG_OVD=1, CLKOUT2_SEL=01, CLKOUT2_DIV=0 and

CLKOUT2_OE=1. The CLKREG_OVD register must be set to 1 before writing to the other registers.

Under default conditions, the GPIO3 pin is configured as the CLKOUT3 function, supporting the FLL

output. For GPIO3 functionality, set CLKREG_OVD=1, CLKOUT3_SEL=01, CLKOUT3_DIV=0 and

CLKOUT3_OE=1. The CLKREG_OVD register must be set to 1 before writing to the other registers.

See “Internal / External Clock Generation” for details of the CLKOUTn_SEL, CLKOUTn_DIV and

CLKOUTn_OE registers. The CLKREG_OVD register is defined in Table 99

(see “Clocking and

Sample Rates

”).

For pins GPIO5 and GPIO6, the pin direction, set by GPn_DIR, must be set according to the function

selected by GP5_FN or GP6_FN.

The characteristics of pins GPIO5 or GPIO6, if selected as an output, may be controlled by setting

GPn_OP_CFG - an output pin may be either CMOS or Open-Drain. When a pin is configured as a

GPIO output, its level can be set to logic 0 or logic 1 using the GPn_LVL field.

GPIO5 and GPIO6 pins can be configured as GPIO inputs can be used to trigger an Interrupt event.

This input may be configured as active high or active low using the IRQ_POL field. De-bouncing of

this input may be enabled using the GPn_DB field. Internal pull-up and pull-down resistors may be

enabled using the GPn_PU and GPn_PD fields. (Note that if GPn_PU and GPn_PD are both set for

any GPIO pin, then the pull-up and pull-down will be disabled.)

The register fields that control the GPIO pins are described in Table 119.

For each GPIO pin, the selected function is determined by the GPn

_FN field, where ‘n’ identifies the

GPIO pin (2, 3, 5 or 6). The polarity of the GPIO outputs can be selected using the GPn_POL register

bits.

When a pin is configured as a Logic Level output (GPn_DIR = 0, GPn_FN = 01h), its level can be set

to logic 0 or logic 1 using the GPn_LVL field.

When the GPIO5 or GPIO6 pin is configured as a Logic Level input (GPn_DIR = 1, GPn_FN = 01h),

its level can be read using the GPn_LVL field.

WM8962B Datasheet(PDF) 175 Page - Wolfson Microelectronics plc

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