WM8962B datasheet(167/295 Pages) WOLFSON

167 / 295 page

WM8962

Rev 4.3

167

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R156 (9Ch)

FLL Control

(2)

8:3

FLL_OUTDIV

[5:0]

000111

FLL FOUT clock ratio

000000 = Reserved

000001 = 2

000010 = 3

000011 = 4

000100 = 5

000101 = 6

…

111110 = 63

111111 = 64

(FOUT = FVCO / FLL_OUTDIV)

1:0

FLL_REFCLK_D

IV [1:0]

FLL Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = Reserved

MCLK (or other input reference) must be

divided down to <=13.5MHz.

For lower power operation, the reference

clock can be divided down further if

desired.

R157 (9Dh)

FLL Control

(3)

8:4

11000

Reserved - Do not change

2:0

FLL_FRATIO

[2:0]

000

FLL FVCO clock ratio

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16

000 recommended for FREF > 1MHz

011 recommended for FREF < 64kHz

R158 (9Eh)

FLL Control

(4)

3:0

0000

Reserved - Do not change

R160 (A0h)

FLL Control

(6)

15:0

FLL_THETA

[15:0]

0018h

FLL Fractional multiply for FREF.

Only valid when FLL_FRAC = 1.

This field sets the numerator (multiply)

part of the FLL_THETA / FLL_LAMBDA

ratio. It is coded as LSB = 1.

R161 (A1h)

FLL Control

(7)

15:0

FLL_LAMBDA

[15:0]

007Dh

FLL Fractional multiply for FREF.

Only valid when FLL_FRAC = 1.

This field sets the denominator (dividing)

part of the FLL_THETA / FLL_LAMBDA

ratio. It is coded as LSB = 1.

Note that it is required that

FLL_LAMBDA > 0 in all cases (Integer

and Fractional modes).

R162 (A2h)

FLL Control

(8)

9:0

FLL_N [9:0]

008h

FLL Integer multiply for FREF

(LSB = 1)

Table 112 FLL Register Controls

WM8962B Datasheet(PDF) 167 Page - Wolfson Microelectronics plc

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