WM8962B datasheet(163/295 Pages) WOLFSON

163 / 295 page

WM8962

Rev 4.3

163

Each of the CLKOUT pins can be enabled or tri-stated using the CLKOUTn_OE registers. When a pin

is tri-

stated, it does not support either the PLL/FLL output or the GPIO function. See “General Purpose

Input/Output (GPIO)

” for more details of the GPIO functions.

A selectable divider is available on each of the CLKOUT pins. When the CLKOUTn_DIV bit is set,

then the respective Clock output is divided by two. Note that, when the selected function is GPIO, then

the CLKOUTn_DIV bit should be set to 0.

The CLKOUT2_DIV and CLKOUT5_DIV registers are controlled automatically under certain

circumstances, as noted in Table 109. The associated control register, CLKREG_OVD, is defined in

the “Automatic Clocking Configuration” section, (see “Clocking and Sample Rates”).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R124 (7Ch)

Analogue

Clocking1

6:5

CLKOUT2_SEL

[1:0]

CLKOUT2 Output Select

00 = PLL2

01 = GPIO2

10 = Internal oscillator

11 = Reserved

4:3

CLKOUT3_SEL

[1:0]

CLKOUT3 Output Select

00 = PLL3

01 = GPIO3

10 = FLL

11 = Reserved

If CLKREG_OVD = 0, then

CLKOUT3_SEL = 10 (FLL) and cannot

be changed by the Control Interface.

If CLKREG_OVD = 1, then

CLKOUT3_SEL = 00 (PLL3) by default,

but the value can be changed via the

Control Interface.

CLKOUT5_SEL

CLKOUT5 Output Select

0 = Internal oscillator

1 = FLL

If CLKREG_OVD = 0, then

CLKOUT5_SEL is controlled by the

GPIO5 pin.

If CLKREG_OVD = 0 and GPIO5 = 0,

then CLKOUT5_SEL = 1 (FLL) and

cannot be changed by the Control

Interface.

If CLKREG_OVD = 0 and GPIO5 = 1,

then CLKOUT5_SEL = 0 (Oscillator) by

default, but the value can be changed

via the Control Interface.

If CLKREG_OVD = 1 then

CLKOUT5_SEL = 0 (Oscillator) by

default, but the value can be changed

via the Control Interface.

R125 (7Dh)

Analogue

Clocking2

CLKOUT3_DIV

CLKOUT3 Output Divide

0 = Divide by 1

1 = Divide by 2

CLKOUT2_DIV

CLKOUT2 Output Divide

0 = Divide by 1

1 = Divide by 2

If CLKREG_OVD = 0, then

CLKOUT2_DIV = 1 (Divide by 2) and

cannot be changed by the Control

Interface.

If CLKREG_OVD = 1, then

CLKOUT2_DIV = 0 by default, but the

value can be changed via the Control

Interface.

WM8962B Datasheet(PDF) 163 Page - Wolfson Microelectronics plc

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