WM8962B datasheet(159/295 Pages) WOLFSON

159 / 295 page

WM8962

Rev 4.3

159

START-UP OPTIONS FOR INTERNAL / EXTERNAL CLOCK GENERATION

The default (start-up) conditions of the WM8962 can be selected using the GPIO5 pin as a hardware

control input. The logic state of the GPIO5 pin during start-up determines the initial value of the

clocking control registers, causing different functionality to be selected for each logic state.

Under specific conditions, some of the registers that are controlled by the GPIO5 pin are locked to

prevent accidental writes to the affected bit(s). In some cases, the GPIO5 pin determines the initial

condition, but the register can still be updated via the Control Interface.

It is possible to unlock all of the clocking control registers, giving full flexibility of the clocking

configuration and to enable GPIO functionality on the GPIO5 pin.

The start-up options for the WM8962 are summarised below. The behaviour of the associated

clocking control registers is summarised in Table 104.

The WM8962 can be configured to generate a CLKOUT5 output as a default start-up condition. Under

default register conditions, with a logic ‘1’ applied to the GPIO5 pin, the CLKOUT5 pin will default to a

Clock output that is derived from the Crystal Oscillator. In this configuration, the Oscillator is enabled

by default, and the CLKOUT5 frequency is the oscillator frequency divided by 2.

Under default register conditions, with a logic ‘0’ applied to the GPIO5 pin, the crystal oscillator is

disabled by default, and no clocks will be present on any of the CLKOUTn pins on start-up.

For full configuration flexibility of the WM8962 Clocking functions, the CLKREG_OVD bit must be set

to ‘1’ in order to select normal read/write access to all clocking control registers.

Note that the GPIO5 pin must be held in a defined logic state (logic ‘0’ or logic ‘1’) during start-up; it

must not be left floating. Normal GPIO5 functionality can be enabled after start-up, after setting the

CLKREG_OVD bit to ‘1’. The GPIO5 pin must be held in a defined logic state (logic ‘0’ or logic ‘1’)

whenever the pin is configured as an input, including whenever CLKREG_OVD = 0.

CLKREG_OVD=0

CLKREG_OVD=1

GPIO5=0

GPIO5=1

MCLK_SRC

00 (MCLK)

01 (FLL) *

00 (MCLK)

OSC_ENA

0 (Disabled) *

1 (Enabled)

CLKOUT3_SEL

10 (FLL) *

00 (PLL3)

CLKOUT5_SEL

1 (FLL) *

0 (Oscillator)

CLKOUT2_DIV

1 (Divide by 2) *

0 (Divide by 1)

CLKOUT5_DIV

1 (Divide by 2) *

0 (Divide by 1)

PLL2_ENA

0 (Disabled) *

1 (Enabled)

PLL3_ENA

0 (Disabled) *

1 (Enabled)

Note - The register settings marked (*) are locked to prevent accidental writes to these registers.

Table 104 Start-Up Options for Internal / External Clock Generation

The register settings described in Table 104 are the initial/default values corresponding to each

GPIO5 condition and each CLKREG_OVD condition. (Note that other clocking configuration registers,

which have no dependency on GPIO5 or CLKREG_OVD, are not listed in Table 104.)

When CLKREG_OVD=0, then the register settings marked (*) are locked to prevent accidental writes

to the associated registers.

When CLKREG_OVD=1, then all of the clocking control fields can be written via the Control Interface.

The MCLK_SRC register is described in the “Clocking and Sample Rates” section. The other registers

referenced above are described later in this section.

WM8962B Datasheet(PDF) 159 Page - Wolfson Microelectronics plc

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