WM8962B datasheet(155/295 Pages) WOLFSON

155 / 295 page

WM8962

Rev 4.3

155

CLASS D, 256K, DC SERVO CLOCK CONTROL

The clocking of the Class D amplifier, DC Servo and other functions is derived from SYSCLK. The

associated dividers are configured automatically by the WM8962.

The Class D amplifier switching frequency is controlled by CLASSD_CLK_DIV. In automatic clocking

mode, the WM8962 uses this divider to generate a Class D clock that is approximately 768kHz. (Note

that there is an additional divide by two in the output stage producing a 384kHz switching frequency.)

A 256kHz clock is required for other circuits, including the Control Write Sequencer. In automatic

clocking mode, the WM8962 uses F256KCLK_DIV to generate a clock that is approximately 256kHz.

The DC Servo clock frequency is controlled by DCSCLK_DIV. In automatic clocking mode, the

WM8962 uses this divider to generate a clock that is approximately 1.5MHz.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

Clocking2

8:6

CLASSD_CLK_

DIV [2:0]

111

Class D Clock Divider

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111= SYSCLK / 16

This field is for read-back only; it is set

automatically and cannot be adjusted.

R30 (1Eh)

Clocking 3

6:1

F256KCLK_DIV

[5:0]

2Fh

256kHz Clock Divider

0d = SYSCLK

1d = SYSCLK / 2

2d = SYSCLK / 3

….

63d = SYSCLK / 64

This field is for read-back only; it is set

automatically and cannot be adjusted.

R56 (38h)

Clocking 4

8:5

DCSCLK_DIV

[3:0]

1000

DC Servo Clock Divider

0000 = SYSCLK

0001 = SYSCLK / 1.5

0010 = SYSCLK / 2

0011 = Reserved

0100 = SYSCLK / 3

0101 = SYSCLK / 4

0110 = Reserved

0111 = SYSCLK / 6

1000 = SYSCLK / 8

1001 to 1111 = Reserved

This field is for read-back only; it is set

automatically by the WM8962.

Table 101 Class D, 256k, DC Servo Clock Control

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