WM8962B datasheet(154/295 Pages) WOLFSON

154 / 295 page

WM8962

154

Rev 4.3

DSP, ADC, DAC CLOCK CONTROL

The clocking of the DSP is derived from MCLK. The clocking of the ADC and DAC circuits is derived

from SYSCLK. The associated dividers are configured automatically by the WM8962.

The DSP clocking rate is controlled by DSPCLK_DIV. In automatic clocking mode, this is configured

automatically by the WM8962 to ensure DSPCLK <= 24.576MHz. (Note that the DSPCLK_DIV divider

is a read-only register; it cannot be written to.)

The ADC clocking rate is controlled by ADCSYS_CLK_DIV. In automatic clocking mode, the WM8962

uses this divider to derive the most suitable SYSCLK / fs ratio, where fs is the ADC sampling rate.

The DAC clocking rate is controlled by DACSYS_CLK_DIV. In automatic clocking mode, the WM8962

uses this divider to derive the most suitable SYSCLK / fs ratio, where fs is the DAC sampling rate.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Clocking 1

10:9

DSPCLK_DIV

[1:0]

DSP Clock Divider

00 = MCLK

01 = MCLK / 2

10 = MCLK / 4

11 = Reserved

This field is for read-back only; it is set

automatically and cannot be adjusted.

8:6

ADCSYS_CLK_

DIV [2:0]

000

ADC Sample Rate Divider

000 = SYSCLK

001 = Reserved

010 = SYSCLK / 2

011 = SYSCLK / 3

100 = SYSCLK / 4

101 = Reserved

110 = SYSCLK / 6

111= Reserved

This field is for read-back only; it is set

automatically and cannot be adjusted.

5:3

DACSYS_CLK_

DIV [2:0]

100

DAC Sample Rate Divider

000 = SYSCLK

001 = Reserved

010 = SYSCLK / 2

011 = SYSCLK / 3

100 = SYSCLK / 4

101 = Reserved

110 = SYSCLK / 6

111= Reserved

This field is for read-back only; it is set

automatically and cannot be adjusted.

Table 100 DSP, ADC, DAC Clock Control

WM8962B Datasheet(PDF) 154 Page - Wolfson Microelectronics plc

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