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WM8962B Datasheet(PDF) 150 Page - Wolfson Microelectronics plc |
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WM8962B Datasheet(HTML) 150 Page - Wolfson Microelectronics plc |
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150 / 295 page  WM8962 150 Rev 4.3 MCLK f/N PLL3 SYSCLK_DIV[1:0] 00 = MCLK 01 = MCLK / 2 10 = MCLK / 4 f/N DAC f/N SYSCLK (12.288MHz max) f/N DC Servo clock f/N Class D switching clock GPIO Clock Output f/N OPCLK_DIV[2:0] 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 3 011 = SYSCLK / 4 100 = SYSCLK / 6 101 = SYSCLK / 8 110 = SYSCLK / 12 111 = SYSCLK / 16 f/N 256kHz clock to Write Sequencer and other circuits Volume update timeout f/N DSP Core f/N f/2 or f/3 MCLK MCLK_SRC selects master clock source (MCLK pin, FLL or PLL3). The PLL3 source, when selected, is divided by PLL_SYSCLK_DIV. The selected source is used to derive SYSCLK, DSPCLK and other clocks automatically. Automatic Clocking Configuration Internal clocks are derived from the master clock source . These are configured using MANUAL_MODE, SAMPLE_RATE, MCLK_RATE, ADC_HP and DAC_HP. DSP Clock Clocking for the Digital Audio Interface and many of the DSP functions is derived from DSPCLK. The master clock source is divided by DSPCLK_DIV to derive DSPCLK. The DSPCLK_DIV divider is configured automatically. Clocking for the ReTune, VSS and HD Bass functions is derived from DSP2CLK. SYSCLK Other internal clocks are derived from SYSCLK. The master clock source is divided by SYSCLK_DIV to derive SYSCLK. The SYSCLK_DIV divider is configured automatically. SYSCLK is enabled by SYSCLK_ENA. ADC / DAC Clocks The ADC clocks are controlled by ADCSYS_CLK_DIV and ADC_HP. The DAC clocks are controlled by DACSYS_CLK_DIV and DAC_HP. The dividers ADCSYS_CLK_DIV and DACSYS_CLK_DIV are configured automatically. DC Servo Clock DC Servo clock is set by DCS_CLK_DIV. The clock frequency is automatically set to around 1.5MHz. Class D Switching Class D switching rate is set by CLASSD_CLK_DIV. The clock frequency is automatically set to around 768kHz. 256kHz Clock The 256k clock for internal functions is set automatically by F256KCLK_DIV. OPCLK Output GPIO output clock frequency is set by OPCLK_DIV. TOCLK, DBCLK Control The slow clock for volume update timeout is enabled by TOCLK_ENA; the frequency is controlled by TOCLK_DIV. Clocking for interrupt de-bounce is enabled automatically when required; the frequency is set by DBCLK_DIV. Digital Audio Interface Control BCLK rate is set by BCLK_DIV in master mode. BCLK rate must be high enough to support the ADC and DAC sample rates. LRCLK rate is set by AIF_RATE in master mode. MCLK f/N Interrupt de-bounce clock FLL BCLK_DIV[3:0] 0000 = DSPCLK 0001 = Reserved 0010 = DSPCLK/ 2 0011 = DSPCLK/ 3 0100 = DSPCLK/ 4 0101 = Reserved 0110 = DSPCLK/ 6 0111 = DSPCLK/ 8 1000 = Reserved 1001 = DSPCLK/ 12 1010 = DSPCLK/ 16 1011 = DSPCLK/ 24 1100 = Reserved 1101 = DSPCLK/ 32 1110 = DSPCLK/ 32 1111 = DSPCLK/ 32 f/N LRCLK BCLK MASTER MODE CLOCK OUTPUTS f/N DSPCLK_DIV[1:0] 00 = MCLK 01 = MCLK / 2 10 = MCLK / 4 DSPCLK (24.576MHz max) f/N PLL_SYSCLK_DIV 00 = PLL3 / 1 01 = PLL3 / 2 (default) 10 = PLL3 / 4 11 = Reserved Automatic DSP Clocking Control SAMPLE_RATE [2:0] MCLK_RATE [3:0] In Automatic DSP Clocking Mode, the DAC, ADC, 256kHz, DC Servo and Class D clocks are configured automatically according to SAMPLE_RATE, SYSCLK_RATE, DAC_HP and ADC_HP. DAC_HP ADC_HP MCLK_SRC SYSCLK_ENA AIF_RATE [10:0] DACSYS_CLK_DIV [2:0] ADCSYS_CLK_DIV [2:0] DCSCLK_DIV [3:0] CLASSD_CLK_DIV [2:0] F256KCLK_DIV [5:0] TOCLK_ENA TOCLK_DIV [2:0] DBCLK_DIV [2:0] OPCLK_ENA BCLK_DIV [3:0] OPCLK_DIV [2:0] DSP Core f/N DSP2CLK (49.152MHz max) ADC f/2 Figure 57 SYSCLK and Internal Clocking Scheme SYSCLK CONTROL The MCLK_SRC register is used to select the source for MCLK. The source may be either the MCLK pin, FLL or PLL3. The PLL3 source, when selected, is controlled by the PLL_SYSCLK_DIV divider. The selected source may be adjusted by the programmable divider SYSCLK_DIV; this is configured automatically by the WM8962 to ensure that SYSCLK <= 12.288MHz. (Note that the SYSCLK_DIV divider is a read-only register; it cannot be written to.) The MCLK_SRC register is controlled automatically under certain circumstances, as described below. The associated contr ol register, CLKREG_OVD, is defined in the following section (“Automatic Clocking Configuration ”). When a logic 1 is applied on the GPIO5 pin, the MCLK_SRC register is set to 01b, selecting FLL as the source. In this case, the MCLK_SRC register is locked to prevent accidental writes to this register. The MCLK_SRC register can be unlocked by setting the CLKREG_OVD bit. When a logic 0 is applied on the GPIO5 pin, the MCLK_SRC register defaults to 00b, selecting MCLK as the source. In this case, the default (00b) is selected on the falling edge of GPIO5; other settings can then be selected by writing to the MCLK_SRC register as normal. |
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